Slow Risetime Driving IO_UPDATE on AD9915 Eval Board

I am using an ADN4668 driven by an ADN4467 to send the IO_UPDATE siignal to the coaxial IO_UPDATE input on the AD9915 Eval Board. The measured risetime is 2 ns. The LVDS signal at the input has a risetime of about 0.5 ns. The spec sheet for the ADN4668 says its output rietime is typically 0.5 ns into a 15 pF load. I removed resistors R130 and R132 to eliminate the connections to U202 and P101A to minimize capacitve loading of the circuit. I don't think this has anything to do with my synchronization issues since lowering the clock frequency to 1250 MHz didn't make things any better, but I know 2 ns is marginal with a 2500 MHz clock. My output is from a hand wired board with about 1" of lead to an SMA connector and a M-M SMA adapter between the board and J101. I am using a wideband 20 GS/s oscilloscope with a 700 MHz bandwidth probe. I just checked it with the output pin disconnected from the load. The best risetime (10% to 90%) is 1.7 ns with no load.