I'm trying to use the AD9957 DDS chip with a microcontroller with an FPGA in between to assist with some clocking. My setup is currently:
MCU -> FIFO -> AD9957 Evaluation board
According to the datasheet, the TXEnable signal is used to gate data on the IQ parallel bus. I am trying to use this to only clock in IQ data at a slower rate that my MCU can handle. I have set the "Hold Last Value" setting in the data assembler so it should hold the last IQ pair I clocked in.
You can see the clocking signals below. PDCLK is running at 4.6MHz (SYSCLOCK = 920MHz, CCI = 50). The FIFO needs an extra clock before the first word - therefore the 3 clocks. So I'm setting TXENABLE high and clocking out a word on the FIFO (a rising RCLK presents a new word on the FIFO output) before PDCLK goes high. And I do this again for the Q word before setting TXENABLE low. When I look at my output however, it seems like the signal is going on and off.
I am not clear on what TXENABLE does exactly. Does it only gate the input data on parallel bus? or does it also control the output RF signal as well? The datasheet only says that the signal gates the data on the bus. Is there some configuration that makes it also affect the output signal?
Clarifying Hold Last Value setting.
[edited by: Aditya.Gaddam at 5:30 PM (GMT 0) on 23 Jun 2020]