AD9957 TXENABLE vs Output

The TxEnable signal is not a clock signal, but rather a control signal. The device actually captures I/Q data on the rising edge of the internal PDCLK signal. The device captures the TxEnable state at the same time that it captures the I/Q data. So, you can think of TxEnable as an extra bit on the bus. The state of TxEnable merely tells the internal logic what to do with the I/Q data.

In general, I/Q data is a stream of data constituting a base band waveform intended for quadrature modulation onto the carrier. That said, the device expects the I/Q data to be a continuous stream of I/Q values where the rate of I/Q pairs constitute the sample rate of the base band signal. TxEnable is a "courtesy" control signal for which the transition from 0 to 1 tells the AD9957 that the current sample is an I-word. As long as TxEnable remains Logic 1, the device treats successive samples (after the 1st) as Q, I, Q, I, etc., which keeps the I/Q data properly segregated in the base band portion of the internal data path. The key point is that TxEnable is not a clock that latches in the data. It is a control signal used by the internal logic.

Under normal conditions, when TxEnable transitions from 1 to 0, it tells the device to stop accepting I/Q data. In which case, the device inserts 0's for I and Q (internally). This is why you see a disturbance in the output. Note there is a register control bit that gives you the option to have the device "remember" the last I/Q pair rather that insert 0's when TxEnable transitions from 1 to 0. However, this is probably of no use to you in this application.

The only exception to the TxEnable going low scenario is when you opt to toggle TxEnable in sync with the I/Q data. However, this mode of operation is of no use to you for this application, either.

The bottom line is that if you want the I/Q samples to occur at a slower rate, then you must use a larger CCI value or reduce the frequency of the system clock, or both. The other alternative is to design your own external base band interpolation stage inserted between the FIFO and the AD9957. That would allow you to operate the FIFO at a lower rate and the interpolation stage would up-sample the FIFO data to the I/Q rate required by the AD9957.

Thank you for the detailed reply! I do have the Hold Last Value setting set. So shouldn't it keep inserting the last IQ pair I clocked in? So if my FIFO changes values (offset binary) at T0, T1, T2...

T0: FIFO is set to 0x0000, TXEN goes high

T0.5: PDCLK rises and clocks in I value

T1: FIFO is set to 0x0000

T1.5: PDCLK rises and clocks in Q value

T2.0: TXEN goes low

T2.5 -> next time TXEN goes high: Shouldn't the DDS output just stay at (-1, -1) or 225deg on the IQ plot as long as TXEN is low? 

If so, my thinking is that this would let me keep TXEN low until I have the next IQ pair ready and loaded into the FIFO. Is that not valid?

Thanks again for the help so far. 

Sincerely,
Aditya

Thank you for the detailed reply! I do have the Hold Last Value setting set. So shouldn't it keep inserting the last IQ pair I clocked in? So if my FIFO changes values (offset binary) at T0, T1, T2...

T0: FIFO is set to 0x0000, TXEN goes high

T0.5: PDCLK rises and clocks in I value

T1: FIFO is set to 0x0000

T1.5: PDCLK rises and clocks in Q value

T2.0: TXEN goes low

T2.5 -> next time TXEN goes high: Shouldn't the DDS output just stay at (-1, -1) or 225deg on the IQ plot as long as TXEN is low? 

If so, my thinking is that this would let me keep TXEN low until I have the next IQ pair ready and loaded into the FIFO. Is that not valid?

Thanks again for the help so far. 

Sincerely,
Aditya

Yes, I think that should work.

I would expect the I/Q plot to step from point to point as you inject each new I/Q pair. However, be aware that the transition from point to point will not occur at the output as a single step. Instead, each I/Q pair will result in a smooth transition from point A to point B consisting of 200 steps (4 x CCI, where CCI=50 in your case).

Just to clarify. So I should allow 200 PDCLK cycles for it to go from point A to B?

- Aditya

No. The transition from A to B occurs over the course of 2 PDCLK cycles. Let me explain...

Each input I/Q pair becomes 4R sub-I/Q pairs (R is the CCI interpolation factor) at the output of the CCI filter -- the result of the base band interpolation process in the AD9957. Note the output of the CCI filter samples at the system clock rate (920Msps, in your case) -- 200 times faster than the expected rate at which you are supposed to deliver I/Q pairs to the input data port.

For example, suppose at time zero, the modulator output is at 90° (based on the current value of I & Q). Now suppose you deliver an I/Q pair to the input that equates to 135°. The output of the CCI filter will start at 90° and smoothly transition to 135° over the course of 200 system clock cycles (which equates to 2 PDCLK cycles). The actual path of the transition is the impulse response of the AD9957's base band interpolation stage (the 2 half-band filters and the CCI filter).

Ah. That makes sense. 

I've been playing with this more and I see that I'm getting a CCI Overflow consistently (even if I clear it) if the Data Assembly Hold Last Value bit is set.

If I turn the Hold Last Value setting off, the CCI overflow can be cleared and stays cleared.

From what I can read about the CCI overflow bit on the forums, it can happen from a jittery SYSCLK or if the interpolation value is changed on the fly. I don't think I have either problem. It only seems to happen when the Hold Last Value setting is set (if it's cleared, it hasn't happened). 

Could something I'm doing with my TXENABLE usage be causing these overflows?

Thanks again for the detailed info. This is definitely helping me understand the workings of the chip better.

Sincerely,

Aditya

Sorry, just came back to reply. I power cycled the evaluation board and then changed the R value back to 50 and now I don't get CCI overflows. I still don't see what I'm programming on the output but at least I see a signal at my programmed frequency and the IQ values ARE changing. 

My IQ values are just (1, 0), (1, 1), (0, 1), (-1, 1), (-1, 0), (-1, -1), (0, -1), (1, -1) where -1 is 0x0000, 0 is 0x1FFFA and +1 is 0x3FFF5 (I have a 16-bit FIFO so D1 and D3 for me are just hardwired to 0). 

Not sure if I'm still having some sort of phase in my timing. Is there any specific point that TXENABLE should go high besides enough time before PDCLK rising to satisfy any hold times?

I feel like I'm getting really close but I guess am still missing something.

- Aditya

I think you will have a difficult time seeing your I/Q changes on the output because they all have the same magnitude (only the phase changes). It would be really difficult to see a phase change on an oscilloscope, unless you have a sophisticated way to trigger a single sweep at just the right time.

However, if you make the 4 I/Q pairs each have a different magnitude, then holding the last value should allow you see the corresponding amplitude change at the output. That is, you should see the carrier amplitude change.

Also, regarding truncated LSBs... You should make truncated LSBs follow the value of the MSB (remember, these are signed values).

I'm using a spectrum analyzer to look at phase over time (we are interested in PSK modulation). So I was hoping to see these changes manifest as a stair/step in the Phase vs Time plot. 

At the risk of sounding dumb, to clarify, the parallel bus has D0 as the LSB and D17 as the MSB correct? I don't have the endianness backwards?

My values on the data port are the following (I am using offset binary mode and not the default two's complement):

-1 => 0x0000 on 16-bit FIFO => 0x00000 on 18-bit parallel bus

0 =>  0x7FFF on 16-bit FIFO => 0x1FFFC on 18-bit parallel bus (D17 = 0, D16-D2 are 1s, D1 = 0, D0 = 0)

+1 => 0xFFFF on 16-bit FIFO => 0x3FFFC on 18-bit parallel bus (D17-D2 are 1s, D1 = 0, D0 = 0)

What I see is something like:

A small GIF of the capture showing more than 1 frame if that helps at all: https://i.imgur.com/IWK0lY3.gif

- Aditya

Yes, D17=MSB and D0=LSB.

If I understand your encoding, then the AD9957 interprets your input as:

+1 → negative full scale (approx.)

0 → positive full scale (approx.)

-1 → 0

In any case, it looks like the phase plot is doing mostly as expected. You are injecting 3 different phases (the red/green plot) and the phase plot is showing 2 different phases plus an oscillation. The oscillation might be due to an I/Q input of -1/-1 which the AD9957 interprets as 0/0 (the origin). The origin equates to NO output (i.e., even the carrier disappears).

Also, make sure the AD9957 output scale factor is set to 1.41 or less. Otherwise, the digital modulator will clip when both I and Q are at full scale positive (or negative), which will adversely affect the output signal.

You might find application note AN-924 helpful.