A way to synchronize multiple AD9857

Hello,

I am trying to work with two of AD9857 DDSs in a synchronized way.

In order to do that, at the same time, REFCLK, DATA, etc,

The problem I find is that latency of output will differ 1 PDCLK  as Figure 33 and Figure 34 in the datasheet,

Is there any good way to synchronize output with PDCLK?

Thanks,

Yong

Parents
  • +1
    •  Analog Employees 
    on Jun 22, 2020 12:29 AM

    Hi Yong,

    The difference between Figures 33 and 34 is that Figure 33 shows the timing for a transmission that starts when PDCLK (SYSCLK/2N) generates a rising edge on the SYSCLK/4N while Figure 34 shows the timing for a falling edge on the SYSCLK/4N. Figure 33 has output that is valid on the falling edge of SYSCLK/4N and is sampled immediately on the next rising edge of SYSCLK/4N while Figure 34 has output that is valid on the rising edge of SYSCLK/4N and is sampled on the next rising edge of SYSCLK/4N that is after one falling edge of SYSCLK/4N. This adds an additional one PDCLK cycle to Figure 34 as compared to Figure 33.

    If we were only talking about a single device, then a solution is to divide PDCLK by 2 (externally) and assert TxEnable only on rising (or falling) edges of the PDCLK/2 signal. That ensures that every burst will have the same latency. However, with two devices, this doesn’t work because the 2nd device may not have the same SYSCLK/2N and SYSCLK/4N relationship as the 1st device. If you have a way to detect that one device is out of sync with the other, then you could assert TxEnable on the rising edge of PDCLK/2 for one device and assert TxEnable on the falling edge of PDCLK/2 for the other device.

    Best regards,

    Mark

Reply
  • +1
    •  Analog Employees 
    on Jun 22, 2020 12:29 AM

    Hi Yong,

    The difference between Figures 33 and 34 is that Figure 33 shows the timing for a transmission that starts when PDCLK (SYSCLK/2N) generates a rising edge on the SYSCLK/4N while Figure 34 shows the timing for a falling edge on the SYSCLK/4N. Figure 33 has output that is valid on the falling edge of SYSCLK/4N and is sampled immediately on the next rising edge of SYSCLK/4N while Figure 34 has output that is valid on the rising edge of SYSCLK/4N and is sampled on the next rising edge of SYSCLK/4N that is after one falling edge of SYSCLK/4N. This adds an additional one PDCLK cycle to Figure 34 as compared to Figure 33.

    If we were only talking about a single device, then a solution is to divide PDCLK by 2 (externally) and assert TxEnable only on rising (or falling) edges of the PDCLK/2 signal. That ensures that every burst will have the same latency. However, with two devices, this doesn’t work because the 2nd device may not have the same SYSCLK/2N and SYSCLK/4N relationship as the 1st device. If you have a way to detect that one device is out of sync with the other, then you could assert TxEnable on the rising edge of PDCLK/2 for one device and assert TxEnable on the falling edge of PDCLK/2 for the other device.

    Best regards,

    Mark

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