AD9912:Signal drift, the output signal is not stable

Hi! I have some probelem when using AD9912. I have an input sysclk of 1GHz(system pll bypassed), and i set the FTW register to a fixed number, but i got a signal whose fequency is not fixed. In theory, the output shouldn't be drifting, are there some issues i failed to notice? Thanks for help!

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    •  Analog Employees 
    on Jun 17, 2020 12:42 PM

    Yes, the output frequency of a DDS is proportional to the system clock frequency (1GHz, in your case). The stability of the output frequency is identical to the stability of the system clock frequency. If sysclk is stable, then the output will be stable.

    With the PLL bypassed we can rule out the possibility of an improperly configured PLL.

    Are you using an AD9912 Evaluation Board or a custom design? How are you measuring the frequency?

  • I have messured the input system clock, and it is very stable, a sine wave of 1GHz. I am using on a custom design and measure the output signal with Spectrum Analyzer. I don't konw whether i set the correct value to disable the internal PLL, are there any suggestions on checking the register value? Thanks for answering.

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