I'm DFAE in Japan. Our customer evaluates AD9914 with FPGA. He wants to verify the setup time IO_UPDATE from FPGA to SYNC_CLK. However SYNC_OUT isn't connected to FPGA in his system. Regarding Both AD9914 and FPGA the reference clock is 3GHz and SYNC_CLK is 125MHz. Therefore he thinks that IO_UPDATE and SYNC_OUT are in sync. But he doesn't know how to check if they are in phase. For example, is it possible to adjust the SYNC_CLK to a certain phase using Master Reset? Or could you tell us if you have a good idea.
Below is the scope shot of SYNC_CLK (yellow), SYNC_OUT (red) and IO_UPDATE (blue). The initial setup is SYNC_OUT was disabled. Then SYNC_OUT was enabled followed by issuing an IO_UPDATE. Phase between SYNC_CLK and SYNC_OUT was measured to be 65 degrees and the setup time of IO_UPDATE was around 26 ns.