I'm trying to setup the AD9915 with a double-ended crystal clock at 156.25MHz.
I'm using a 2x Divider, and N=16 which should set the PLL output to 2.5GHz.
Unfortunately After VCO Calibration and reading lock status bit, I'm not achieving lock.
If I set N to 15 (2.34GHz) then I am able to achieve lock.
If I set 8xDivider and N=61 (2.38GHz) I am also able to achieve lock.
If I try N=62 (2.42GHz), I can unable to achieve lock.
I'm attempting to get the PLL frequency into the 2.4-2.5GHz region described on page 28 of the datasheet.
When running at 2.38GHz SYSCLK, I'm also seeing very low (-54dBm) sine output from the DDS Core at when setting to 800MHz over Direct Mode.
I have tried setting the Amplitude to full using Direct Mode, Profile Mode, and also OSK Mode, but all of these attempts result in signal disappearing.
I don't know if this is due to the SYSCLK being out of spec, but it's worth mentioning.
Any help with these matters would be much appreciated.
Are you using the evaluation board and software?
We are using a custom board, but the circuit design is copied from the evaluation board with the same component values.
We are not using the software but programming via an embedded controller.
We had previously used the software to validate the early system design and produce the programming register values we are currently trying to use on the embedded board.
I tried the same divider and N value combinations that you used for the PLL using the AD9915 evaluation board and I was able achieve PLL lock in every combination. The output and SYSCLK are also correct. May I know the SYSCLK frequency that you are obtaining for the divider and N value combinations that are not locking?