In the DS figures 42-45 two modes are illustrated Clock Stall LOW and Clock Stall HIGH. I could not find any information on how can I change it and what is the default setting. Also on the page 38 in the 3rd paragraph it says that serial interface port can be configured as 2-wire (SDIO) and 3-wire (SDIO and SDO) interface AFAIK there is no further information on how to set and what is a default configuration.
VyacheslavLi said:Also on the page 38 in the 3rd paragraph it says that serial interface port can be configured as 2-wire (SDIO) and 3-wire (SDIO and SDO) interface AFAIK there is no further information on how to set and what is a default configuration.
CFR1 bit 1 logic 0 is a default configuration that sets 2-wire interface and logic 1 is a 3-wire interface.
Regarding clock stall low/high, there is nothing to program. Clock stall relates to the SCLK signal, which you control via an external controller/processor. The low/high stalling is just a matter of whether you make the external controller hold SCLK low or high during programming sequences (per the diagrams).
Regarding 2- or 3-wire operation, the device defaults to 2-wire (CFR1=0). That is, SDIO is a bidirectional input/output serial pin and SDO is unsed.
In 2-wire mode, when the SPI instruction byte indicates WRITE, then SDIO becomes an input for the data that follows during the write operation. Conversely, when the SPI instruction byte indicates READ, then SDIO becomes an output during the read operation. Otherwise, SDIO is tristate.
In 3-wire mode (which requires that you program CFR1=1), the SDIO pin is an input pin only. Hence, write operations require you to send serial data to the SDIO pin and read operations require you to observe serial data at the SDO pin.
Thanks for clearing it up. I thought that stall high/low changes whether the bit is read on a raising/falling edge.