PLL INITialization

HI Team,

iam trying to generate 20Mhz SPI clock and also 350MHZ CCLK .as per calculations in my code CCLK =( 25MHZ * PLLM14* 2)/2 =350Mhz then PCCLK =175Mhz.

In my hardware cclk configured to 400MHz as CLK_CFG bits  set sto '10'. 

as per formula my SPI clk must be generate 175/(4*BAUD-5) =8.75MHZ but in my case its generating 12.5Mhz its not generating as per calculations .

Please provide technical information to reduce cclk down to 350MHZ.

void Init_PLL(void)
{
int i, pmctlsetting;
pmctlsetting = *pPMCTL;
pmctlsetting &= ~PLLM63; // Clear the previous PLL multiplier
*pPMCTL= pmctlsetting;
pmctlsetting &= ~PLLD16; // Clear the previous PLL devider
*pPMCTL= pmctlsetting;
//pmctlsetting &= ~INDIV; // Clear the INDIV bit
// CLKIN= 25 MHz, Multiplier= 16, Divisor= 2, CCLK_SDCLK_RATIO 2.5.
// Fcclk = (CLKIN * 2 * M) / (N * D)
// VCO frequency = 2*fINPUT*PLLM = 2*25*16 = 800 <= fVCOmax (800 MHz)
// M = 1 to 64, N = 2,4,8,16 and D = 1 if INDIV = 0, D = 2 if INDIV = 1
//pmctlsetting |= INDIV; // or set the INDIV bit
pmctlsetting= PLLM14|PLLD2|SDCKR2_5|DIVEN;
*pPMCTL= pmctlsetting;
pmctlsetting|= PLLBP; //Setting the Bypass bit
*pPMCTL= pmctlsetting; // Putting the PLL into bypass mode
        pmctlsetting &= ~DIVEN; //Clearing the DIVEN bit
       *pPMCTL= pmctlsetting; // Putting the PLL into bypass mode
//Wait for around 4096 cycles for the pll to lock.
for (i=0; i<5000; i++)
asm("NOP;");
pmctlsetting = *pPMCTL;
pmctlsetting &= ~PLLBP;          //Clear Bypass Mode
*pPMCTL = pmctlsetting;
//Wait for around 15 cycles for the output dividers to stabilize.
for (i=0; i<16; i++)
asm("NOP;");
}
void spi_init(unsigned int SPI_Flag)
{
*pSPICTL = (TXFLSH | RXFLSH) ;         /* Configure the SPI Control registers. Flushing the TX and RX buffers */
    *pSPIFLG = 0;                          /* First clear a few registers */
    *pSPIBAUD = 5;                   
*pSPIFLG = (SET_DSXEN_BITS | SPI_Flag);  /* Setup the SPI Flag register using the Flag specified in the call */
*pSPICTL = (SPIEN | SPIMS | WL16 | MSBF  | CPHASE | CLKPL | TIMOD1 | SMLS | GM); /*CPHASE | CLKPL | TIMOD2 |*/ /* Now setup the SPI Control register */
*pSPIDMAC = 0;
}