I am trying to use AD9915 evaluation board for fast frequency, phase and amplitude modulation. The idea is to serial program 8 available profiles and then jump from one to another. If we will need more configurations available we want to reprogram profiles before ahead and jump from profile to another at a precise time.
My concern is that I am new and could not understand or find some information from the Datasheet. I was able to control the DDS via USB following Evaluation Board user guide.
Could you please explain me explicitly how can I set up the system and how can I verify that a simple profile 0 frequency is set to 100 MHz for example. I hope that this will be very useful to others as well as many students without a specific background are intended to use DDS and program them a lot. We are using 2.4 GHz external reference clock.
Several question that I already have:
1) As far as I understand Sync_CLK is not used in serial programming. Am I right?
2) How the Sync_CLK is obtained? When using GUI and controlling via USB the Sync_CLK is shown in a right top corner as 2.4 GHz and could not be changed. Reference clock is 2.4 GHz. However, I with a spectrum analyzer I measured it to be 300 MHz. If I would need to change Sync_CLK, is there a way to do it?
Thanks in advance
Good day to you. You mentioned profile 0, the term "profile" simply means as a configuration of the DDS. This is a coalescence of the three parameters that you can set for the output: frequency, amplitude, and phase which constitutes as a configuration. This is manifested on the datasheet and I'd like to show it below.
As an example, let us say you would like to use profile 1. The data sheet shows that there are 2 registers, each having a length of 4 bytes that acts as container for your intended frequency, amplitude, and phase of the signal.These set of registers is described as profile 1.Most of the times, our product would contain 8 profiles which are mapped to the the 3 profile pins of the DDS. The advantage of having this architecture is that you can have presets of your signal in the DDS and you can switch between these presets by just using the pin mapping.
1) Yes SYNC_CLK is not used for serial programming. It serves as a reference for the rate of the state-transition of the device. Thus it means that, the fastest rate you can change the preset, or profile, is the frequency of the SYNC_CLK.
2) SYNC_CLK is not actually identical to the SYSCLK, which is 2.4 GHz in your case.It operates with a frequency sub-multiple of the SYSCLK. It should be 1/16 of the SYSCLK. The only way to change it is by changing the ref clock.
I hope this helps.
Up to now I was able to control AD9915 via GUI with USB.
I did the following:
P204, P203, P202 set to disable
IOCFG0-IOCFG3 (function pins) set to 0001 (to choose serial programming mode)
EXTPDCTL - grounded
RESET-BUF - grounded. I maser reset once in the beginning and then grounded it.
CS - grounded
SYNCIO - I make it HIGH to make sure that the pointer of the serial programming is set to the very first bit and then ground it.
I send the following pattern to SCLK and SDIO pins. Then I initiate update by sending 0.5 s pulse to IOUPDATE-BUF pin expecting that the J100 signal will go away. But it doesn't. Could you please tell me what am I doing wrong. If I will be able to turn off SYNCCLK I will be able to do everything I need for my application. I am also intended to write some step by step guidance for people not familiar with this kind of stuff to be able to get started and use this versatile DDS.
Thanks for your support!
I suggest to refer to the wiki of this product if you are planning to create a step by step guide for the evaluation board. Please refer to this link if you wanted to visit the wiki. It contains some guidelines on how to use the board that isn't elaborated on the datasheet.
In turning off the SYNC_CLK, you can use this register to disable it:
There are two things that I recommend;
1.) By default, the SPI configuration of AD9915 uses one pin for write and read. For convinence I suggest to make the AD9915 use two pins instead, one pin for read and one pin for write. It is easier to debug with this configuration.
2.) I discourage to latch CS to logic low indefinetely because it might cause the part to fase trigger or perform an unwanted SPI transaction. If possible, if the SPI lines are n't use, put this pin in the high logic.
LouijieC said:Please refer to this link if you wanted to visit the wiki
My problem is that I have already read it I think 5 times...
LouijieC said:In turning off the SYNC_CLK, you can use this register to disable it:
When I supply the signal that I mentioned don't I set the register SYNC_CLK to 0 making it disabled?
Could you please tell me what should I do to be able to make SYNC_CLK disable. What exactly signal should I supply to SCLK and SDIO pins. I am newbie and not sure whether I understood how SPI works or not because I could not turn off SYCN_CLK.
VyacheslavLi said:I send the following pattern to SCLK and SDIO pins.
Is this pattern wrong? I thought that I send first the instruction byte containing the address and then if I send 32 byte of zeros I will set SYNC_CLK register to zero, which is disable according to DS.
LouijieC said:If possible, if the SPI lines are n't use, put this pin in the high logic.
If I understood correctly I should make CS, SYNCIO and SDO high as well, right?
LouijieC said:For convinence I suggest to make the AD9915 use two pins instead, one pin for read and one pin for write
I could not find how to do it. Could you please explain how to set 3-write interface?
LouijieC said:I discourage to latch CS to logic low indefinetely because it might cause the part to fase trigger or perform an unwanted SPI transaction.
Currently I am using only one chip. In my case does it make sense to tie CS pin to low permanently?