DDS: ramped chirp generation possible?

Hello,

Is there any built-in functionality, on any DDS's, that could generate a frequency sweep which has a gradual decrease in the sweep amplitude?

Specifically, I'd like the generation center at 120.0 MHz; sweep +/-2 MHz at 10 kHz; but gradually (continuously) ramp down that sweep (but maintaining the same sweep rate), over the course of a few seconds or so, to 120.0 MHz (single frequency).

I have AD9914/15's eval boards and they can certainly do the constant-amplitude sweep, but gradually decreasing the sweep range does not seem possible over SPI, without clumsily sending it a million update pulses, which would be limited by my microcontroller's abilities; it seems it'd require a more complex parallel programming method, perhaps even an FPGA, which I am hoping to  avoid.

Paul

  • 0
    •  Analog Employees 
    on Dec 8, 2019 11:05 PM

    Hi Paul,

    it seems it'd require a more complex parallel programming method, perhaps even an FPGA, which I am hoping to  avoid.

    Before I read your statement, this was actually the first thing I have in mind. What I could think off is to use the Ramp Generation Funcitonality of the DDS. You can use the ramp funtionality which you can declare at the start and end frequency of the registers then synchronously generate the sweep. The mechanism behind this functionality is it operates along with the SYNC_CLK. So you can define the rate and the step size of your sweep if you use this feature relative to the frequency of the SYNC_CLK. Using this to your application and with the constraint of using the SPI channel, would mean that you have to continuously update the registers and whenever you wanted to decrease the sweep range. So the rate of the decrease of the sweep range would depend on the time it took to update the neceessary values in the ramp registers.

    Best Regards

    Louijie

  • 0
    •  Analog Employees 
    on Dec 9, 2019 2:22 PM

    The AD9910, in addition to frequency sweep capability, offers an "automatic ramped OSK (Output Shift Keying)" mode. In this mode, you can program:

    • the amplitude step size (1, 2, 4 or 8 LSB)
    • a 16-bit step rate (in units of 4 times the system clock period)
    • the maximum amplitude value (14-bit resolution)

    The maximum system clock rate of the AD9910 is 1GHz, equating to a 1ns system clock period. Hence, the longest possible step period is 1ns x 4 x 2^16, or 262μs. If the maximum amplitude value is full scale (14 bits) and the step size is 1 LSB, then the longest possible amplitude ramp time is 262μs x 2^14, or 4.3s (for a 1GHZ system clock) .

    The only caveat is that the automatic ramped OSK function triggers via an external pin. Therefore, you would need to synchronize the OSK pin with the start of your frequency sweep.