Hello: ADI technical engineer.
Excuse me: the DAC calibration of ad9914 mainly corrects those functions of the chip.
How long is the best time for DAC calibration after power on, and how long is the internal program loading of ad9914.
The usage is as follows:
1. The reference clock of DDS is 3.5GHz;
2. DAC calibration shall be carried out 0.5ms after FPGA program runs normally;
3. DAC output always switches between 720MHz and 720MHz + 500Hz.
The fault phenomenon is as follows:
1. After power on, 720MHz ± 8.9khz spurious is good or bad, sometimes 72dbc, sometimes 47dbc.
2. When the frequency of 100MHz constant temperature crystal is doubled to 3.5GHz and the signal source (R & s ® sma100b) provides 3.5GHz, the above strip phenomenon will occur (because the frequency stability of constant temperature crystal is poor when it is powered on, two methods are used for testing).
3. The test picture is as follows
4. The modification is as follows
② 3.5GHz from 100MHz constant temperature crystal oscillator frequency doubling
72 DBC for 720MHz ± 8.9khz, but 25 DBC for 1K, 17 DBC for 10K, and 10 DBC for 10K,
The test picture is as follows
Good day to you.
In reference to the datasheet, the suggest DAC calibration time is tcal = 469.632/sampling_frequency. However this has a constraint of having a maximum time limit of 135us. These guidelines can be found in page 6 and page 20 of the datasheet.
Lastly, may I know what you mean by:
andlyjun said:how long is the internal program loading of ad9914
Are you referring to the loading of the values to the registers. If that is the case it would be the same as the rate of the SYNC_CLK, which is 1/24 of the sampling rate.
I'm talking about how long the ad9914 can be powered on to write data
I'm talking about how long can I write data after the ad9914 is powered on