AD9959 - SPI

Hello ! My question involves a reply that I wrote recently to an ADI thread, but that thread was from 2014 or so, and may be inactive even though I managed to write a reply to it today.

The thread is : https://ez.analog.com/dds/f/q-a/29416/ad9959-spi-problem

And my question was:

Page 31 of the Revision B pdf actually writes this: "All data written to the AD9959 is registered on the rising edge of SCLK. Data is read on the falling edge of SCLK (see Figure 43 through Figure 49)." --- and Fig. 42 does indeed reflect what is written.

However, Fig. 43 appears to indicate the OPPOSITE. Figure 43 (for single-bit operation) is showing data is being 'registered' on the falling edge of SCLK, and is then 'read' on the rising edge of SCLK.

Here, I assume 'registered' or 'registration' means placing or loading the bit ----- in order to get the voltage level ready or prepared. And I assume that 'read' means the data bit (voltage level) getting sampled or captured.

Does this mean there is discrepancy in the documentation? If there is discrepancy, then which part of the information is correct?

The AD9959 pdf document is : www.analog.com/.../AD9959.pdf

Thanks all!



minor edit
[edited by: KennyL at 11:09 PM (GMT 0) on 13 Oct 2019]
  • Hello ---- this is an update. All of this time - I was following the exact words written on Page 31 - about data being read on the falling edge of SCLK. This turns out to be incorrect information.

    It turns out that the correct information is contained in Fig. 43. The correct information should be that the data is actually read (sampled) on the RISING edge of the serial clock, SCLK.

    If those written words on page 31 are truly in error, then that could definitely throw some people off ---- until they compare those written details with the figures. However, Fig. 42 and Fig 43 appear to conflict with each other.

    To clear things up - the data going to the AD9959 is indeed read (sampled) on the rising edge of the serial clock. Not on the falling edge. Fig. 42 is showing the wrong details, while Fig 43. is showing the correct timing details. Thanks all.