AD9910 DRG accumulator when changing between destinations


Wondering if the DRG accumulator maintains the number of steps it has taken when switching between ramp destinations. For instance, if I ramp frequency from 10 to 100 MHz, then change the STP to sit at 100 MHz and set the DRG destination and information to phase on the same IOUpdate pulse, will the DRG accumulator maintain the number of steps taken during the Frequency ramp stage? Is it a good practice to set and reset the DRG clear bit, or is that automatic when the destination changes? 


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