Wondering if the DRG accumulator maintains the number of steps it has taken when switching between ramp destinations. For instance, if I ramp frequency from 10 to 100 MHz, then change the STP to sit at 100 MHz and set the DRG destination and information to phase on the same IOUpdate pulse, will the DRG accumulator maintain the number of steps taken during the Frequency ramp stage? Is it a good practice to set and reset the DRG clear bit, or is that automatic when the destination changes?
Okay I have one more question related here. Does the DRG accumulator continually add the DRSS frequency step to the current FTW every DRR time step, or does it act as a counter which multiplies its value by the DRSS and adds to the DRL lower limit? From playing around, it seems the latter is the case, but I just want to be sure. I'm running into trouble with frequency continuity when programming multiple frequency ramps sequentially.
Your first assumption is correct: It is an accumulator, so it adds the programmed step frequency each time the step counter times out (per the programmed ramp rate register values).
EDIT: Deleted comment about Eval. Bd. software bug. The bug relates to the AD9914, not the AD9910.
( I'm using a built-in FPGA on the FlexDDS from wieser labs.) I thought it should behave like that, but could you shed some light on the behavior I'm seeing as described before? that is: If I want to sweep from 1 MHz to 2 MHz, then to 3 MHz, if I change both of the DRL limit parameters (same steps) after the first sweep, I pop to the end of the second sweep on the IO update. It's like the DRG knew it was at the end of the first sweep, then jumps to the end of the second sweep once both the limits change on the IO update. This doesn't happen if I leave the lower limit and only increase the upper limit. I really appreciate your expertise here!
You are probably somehow confusing the internal state machine. What, exactly do you want to accomplish? Sweeping from 1-2MHz, then 2-3MHz seems like an odd sequence.
What about setting the sweep from 1-3MHz, but assert DRHOLD at the appropriate time to freeze the sweep at the 2MHz point. Then deassert DRHOLD when you want to finish the sweep. Of course, you'll need to experiment with the timing of DRHOLD to get it just right.
So the goal is to do a string of sweeps between a list of arbitrary frequencies, with continuous phase and frequency. We work with cold atoms, so these continuities are crucial for the experiment. The 1->2, 2->3 just illustrates the issue I'm seeing. I'm having some success changing single ramp limits, so I'll come back when I have more questions. Thanks!
I think I know what's going on with regard to your "inter-sweep" problem...
Upon reaching the 2MHz upper limit of the 1st sweep, the state machine halts the step counter. However, as soon as you raise the upper limit for the 2nd sweep, the state machine (which is effectively still in the midst of an up-sweep) is no longer constrained by the upper limit and takes off. I expect this is normal behavior considering the original design goals.
You might consider using the Parallel Data port for sweeping. Then you'll have full control of the time domain dynamics of the output frequency. The only drawback is that the Parallel Data port may not have sufficient frequency resolution depending on exactly what sweep ranges you choose (see the data sheet for details).