There is no specification in the AD parallel programming mode description that it is required to drive the profile pins (PS[2:0]) with the profile number when reading the profile registers.
However, for the serial programming mode there is a description of that saying " ... to read back any profile register (0x0B to 0x1A), the three external profile pins must be used. For example, if the profile register is Profile 5 (0x15), the PS[0:2] pins must equal 101.".
In the data sheet there is a figure showing that the parallel programming and serial programming mode are connected to the registers more or less the same way, so maybe the parallel programming mode description simply lacks a description for control of the profile pins (PS[2:0]) when reading the profile registers.
Is there anyone that can say if the profile pins (PS[2:0]) must or need not be driven when reading the profile registers using parallel programming mode ?
Thanks in advance.
Although I cannot definitively answer that question, I'm fairly certain the PS2:0 requirement only holds for SPI reads (that is, only when F[3:0]=0001).
I just found an engineering document indicating that the PS[2:0] pins serve as an address offset to the Profile registers for read operations. It seems to imply that this is true regardless of the mode by which one reads the Profile registers.
Thanks a lot for your effort; this is a much better way to get the design right than doing trial and error ;-)
Btw. do you have a reference to the engineering document that describes use of PS[2:0] as address bits ?
Best regards Morten
Only that it is an internal design document and, as such, restricted to internal use.
Thanks, that sounds like a good reference ;-) I was not aware that you are an insider. Thanks a lot for the help.