AD9957_QDUCMODE+PDCLK rate control bit

Hello

I have a question about AD9957.

I run AD9957 with "QDUCMODE + PDCLK rate control bit".

The data sheet has the following description.

「 This causes rising edges on PDCLK to latch incoming I-words and falling edges to latch incoming Q-words. Again, the edge polarity assignment is reversible via the PDCLK Invert bit.」

What is the PDCLK voltage value at which data is latched at this time?

We think that it has hysterical characteristics at the rise and fall.

Also, can you provide information if there is a timing chart figure in MODE above?

Please tell me.

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  • 0
    •  Analog Employees 
    on Sep 4, 2019 2:43 AM over 1 year ago

    Hi Baggio,

    I believe that your questions are related and are inclined more on the timing guidelines of the QDUCMODE.

    What is the PDCLK voltage value at which data is latched at this time?

    can you provide information if there is a timing chart figure in MODE above?

    As guidelines in using the QDUCMODE, I'd like to refer this thread which was answered by KennyG. Though the thread contains a question that is different from your current concern, I believe that there is a part in the discussion that is relevant to your current inquiry. Thus I'm gonna iterate that part below:

     The primary requirement for using the AD9957 in QDUC mode is to ensure the data supplied at the parallel port is at the correct sample rate. The parallel port data rate (PDCLK) is directly dependent on the DAC sample rate (Fs) and the CCI interpolation factor (R) as: PDCLK = Fs/(2R).

    For the timing diagram, I'd like to know if the one that was provided by the datasheet contains enough information. This is depicted below.

    I hope this helps.

    Best Regards

    Louijie

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  • 0
    •  Analog Employees 
    on Sep 4, 2019 2:43 AM over 1 year ago

    Hi Baggio,

    I believe that your questions are related and are inclined more on the timing guidelines of the QDUCMODE.

    What is the PDCLK voltage value at which data is latched at this time?

    can you provide information if there is a timing chart figure in MODE above?

    As guidelines in using the QDUCMODE, I'd like to refer this thread which was answered by KennyG. Though the thread contains a question that is different from your current concern, I believe that there is a part in the discussion that is relevant to your current inquiry. Thus I'm gonna iterate that part below:

     The primary requirement for using the AD9957 in QDUC mode is to ensure the data supplied at the parallel port is at the correct sample rate. The parallel port data rate (PDCLK) is directly dependent on the DAC sample rate (Fs) and the CCI interpolation factor (R) as: PDCLK = Fs/(2R).

    For the timing diagram, I'd like to know if the one that was provided by the datasheet contains enough information. This is depicted below.

    I hope this helps.

    Best Regards

    Louijie

Children
  • Hello Louijiec

    Thank you for the reply.

    The timing chart you provided is shown in Figure 31 of the data sheet.

    I am watching this.

    However, I think this timing chart is for QDUCMODE.

    I want to operate in the following modes described in this data sheet.

    The timing chart at this time was not described in the data sheet.

    Could you give me a timing chart at this time if possible?

    I am also considering this, but it would be helpful if you could tell me the voltage value at which data is latched by PDCLK.

    I'm sorry but thank you.

  • 0
    •  Analog Employees 
    on Sep 5, 2019 1:50 AM over 1 year ago in reply to baggio

    Hi Baggio,

    In the mode that you wanted to operate, these are the things that are important to note:

    1.) Frequency of PDCLK is reduced by a factor of two.

    2.) I-words are latched to the rising edge of PDCLK

    3.) Q-words are latched to the falling edge of PDCLK

    I made a diagram to express and these are illustrated below: (Edge polarity is reversible via the PDCLK Invert bit)

    With this, please still observe the tds and tdh requirements indicated by the datasheet. Since PDCLK operates at 3.3 Voltage, For your question in the voltage that it would latch into, I'll refer to the specification for the CMOS logic in the datasheet.

    Best Regards

    Louijie

  • Hello Louijiec

    Thnk you very much.

    I was very saved. 

    I will use this information 

    I look forward to working with you.

  • Hello Louijiec

    I have additional questions.

    It would be helpful if you could answer.

    You are listed that IQ data acquisition timing is as follows when in state "QDUCK+PDCLK rate control bit".

     1.) Frequency of PDCLK is reduced by a factor of two.

     2.) I-words are latched to the rising edge of PDCLK

     3.) Q-words are latched to the falling edge of PDCLK

    However, if you look at the explanation of “PDCLK Invert” on page 57 of the data sheet, you will find the following.

    This content is different from P21 of the data sheet.

    Is the description on page 57 incorrect?

  • 0
    •  Analog Employees 
    on Sep 11, 2019 2:23 AM over 1 year ago in reply to baggio

    Hi Baggio,

    Thank you for pointing it out and I apologize for the confusion it brought up. I will check and verify this discrepancy. Then I'll get back to your inquiry.

    Best Regards

    Louijie