AD9957_QDUCMODE+PDCLK rate control bit

Hello

I have a question about AD9957.

I run AD9957 with "QDUCMODE + PDCLK rate control bit".

The data sheet has the following description.

「 This causes rising edges on PDCLK to latch incoming I-words and falling edges to latch incoming Q-words. Again, the edge polarity assignment is reversible via the PDCLK Invert bit.」

What is the PDCLK voltage value at which data is latched at this time?

We think that it has hysterical characteristics at the rise and fall.

Also, can you provide information if there is a timing chart figure in MODE above?

Please tell me.

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  • 0
    •  Analog Employees 
    on Sep 4, 2019 2:43 AM

    Hi Baggio,

    I believe that your questions are related and are inclined more on the timing guidelines of the QDUCMODE.

    What is the PDCLK voltage value at which data is latched at this time?

    can you provide information if there is a timing chart figure in MODE above?

    As guidelines in using the QDUCMODE, I'd like to refer this thread which was answered by KennyG. Though the thread contains a question that is different from your current concern, I believe that there is a part in the discussion that is relevant to your current inquiry. Thus I'm gonna iterate that part below:

     The primary requirement for using the AD9957 in QDUC mode is to ensure the data supplied at the parallel port is at the correct sample rate. The parallel port data rate (PDCLK) is directly dependent on the DAC sample rate (Fs) and the CCI interpolation factor (R) as: PDCLK = Fs/(2R).

    For the timing diagram, I'd like to know if the one that was provided by the datasheet contains enough information. This is depicted below.

    I hope this helps.

    Best Regards

    Louijie

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  • 0
    •  Analog Employees 
    on Sep 4, 2019 2:43 AM

    Hi Baggio,

    I believe that your questions are related and are inclined more on the timing guidelines of the QDUCMODE.

    What is the PDCLK voltage value at which data is latched at this time?

    can you provide information if there is a timing chart figure in MODE above?

    As guidelines in using the QDUCMODE, I'd like to refer this thread which was answered by KennyG. Though the thread contains a question that is different from your current concern, I believe that there is a part in the discussion that is relevant to your current inquiry. Thus I'm gonna iterate that part below:

     The primary requirement for using the AD9957 in QDUC mode is to ensure the data supplied at the parallel port is at the correct sample rate. The parallel port data rate (PDCLK) is directly dependent on the DAC sample rate (Fs) and the CCI interpolation factor (R) as: PDCLK = Fs/(2R).

    For the timing diagram, I'd like to know if the one that was provided by the datasheet contains enough information. This is depicted below.

    I hope this helps.

    Best Regards

    Louijie

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