I have a question about AD9957.
I run AD9957 with "QDUCMODE + PDCLK rate control bit".
The data sheet has the following description.
「 This causes rising edges on PDCLK to latch incoming I-words and falling edges to latch incoming Q-words. Again, the edge polarity assignment is reversible via the PDCLK Invert bit.」
What is the PDCLK voltage value at which data is latched at this time?
We think that it has hysterical characteristics at the rise and fall.
Also, can you provide information if there is a timing chart figure in MODE above?
Please tell me.