AD9914 / AD9915 - Less Spurs with Programmable Modulus and Avoidance of Phase Trunca

The AD9914/15 uses a 17-b phase-to-amplitude converter (PTAC). That is, the 17 MSBs of the accumulator feed the PTAC. However, the phase offset adjustment feature is constrained to 16-b.

That said, any FTW having a non-zero bit within its 15 LSB positions will exhibit phase truncation spurs. This is true for normal and programmable modulus operation.

Programmable modulus provides additional tuning frequencies not available with a standard 32-b FTW. However, programmable modulus guarantees the existence of phase truncation spurs, because it modulates the LSB of the 32-b FTW applied to the PTAC. That said, programmable modulus exhibits dynamic phase truncation spurs, because the FTW is modulated rather than being static.

Unknown said:

17-b phase-to-amplitude converter (PTAC).

Oh, sorry, my mistake. Thanks for the correction.

Regarding the phase truncation spurs from the 17 bit truncation, there is the ADIsimDDS tool, where I can calculate at least the most dominant phase truncation spurs (do you know if it is possible to show more than only the singla most dominant one?).

Is there also a tool that shows the sours generated by the programmable modulus?

You say the programmable modulus guarantees the existance of spurs, but so does the usage of the 15 LSBs of the FTW. I can immagine that there may be output frequencies where you have to use at least one of these two options and where the spurs generated by the programmed modulus might be lower (in energy) than the ones generated by the 17 bit phase truncation or just at a less problematic frequency.

Is there a table where one can easily see the width (in bits) of the look-up-table for the various DDS chips? Wouldn't it be good to include such a column in the selection table / parametric search?

Although it is possible to predict "normal" phase truncation spurs completely (frequency and magnitude), the computations are prohibitive. This is why ADIsimDDS shows only the primary phase truncation spurs. In fact, I provided the math that ADIsimClk uses for computing the primary phase truncation spurs. You can find details in application note AN-1396.

There is no tool for showing phase truncation spurs in the context of programmable modulus.

Yes, having non-zero bits in the truncated portion of the FTW guarantees phase truncation spurs. However, because the FTW is static, the spurs are completely deterministic (though predicting spur location and magnitude is extremely computation intensive).

As stated in my previous post, programmable modulus modulates the LSB of the 32-b FTW yielding phase truncation spurs that vary with time, which further complicates predicting spur location and magnitude.

Ah, now I see.

The programmable modulus adds to the LSB and therefore always introduces the truncation spurs and lets them even be dynamic.

Programmable modulus would only be a possible alternative if one could make it modify only those bits that do not get truncated.

Like if it would start on the "LSB" of the 17 MSBs.

Regarding the exact calculations, how "prohibitive" would they be, given modern computing possibilities?

Edit: There seems to be a module for Scilab making it capable of octuple precision math.

Actually, I should clarify a comment in my previous post. I stated that programmable modulus "modulates" the LSB of the 32-b FTW. That's not exactly true. If it were, then it would be a form of frequency modulation, which is not the case.

Instead, programmable modulus uses the nearest 32-b FTW below the desired frequency and periodically injects an LSB directly into the accumulator. This slightly advances the phase of the accumulator so that the resulting frequency is exactly the desired frequency. Hence, it's more like phase modulation, but always in the positive direction.

Believe me, the calculations for DDS spurious are prohibitive. It's not just about the precision, it requires computations on huge sets of numbers. Most computers (consumer/business) must grind away for hours to yield results (that's assuming they don't run out of memory space).

I'm quite sure that I underestimate how complicated such a calculation would be, but looking at "A Technical Tutorial on Digital Signal Synthesis" by Analog Devices from 1999, on page 19 and following pages, it does not look very difficult.

Compute the GRR,

Compute the ETW,

Compute the truncation word capacity,

Compute the number of overflows (GRR/(capacity/ETW)

Compute the fundamental frequency of the truncation word sawtooth (Fs times (ETW/capacity)

Compute all the harmonics of the frequency of the truncation word sawtooth from 1st harmonit to GRRst harmonic

Fold each of these harmonics into the Nyquist band at Fs and it's harmonics

Done

I might try to calculate a few examples when my headaches have settled a bit. But as GRR can be huge with modern DDS chips, we may be talking about a huge number of spurs that would have to be calculated.

Surprise! You're talking to the person who wrote it.  ;^)

Truth is, DDS spurious was not completely understood at the time. The section of the "Tutorial" that you reference was my stab at identifying spur locations. The algorithm is useful, but incomplete.

In the early 2000's a doctoral thesis by Arthur Torosyan at Univ. of Calif. provided a mathematical analysis of DDS spurious that accurately predicts the frequency and magnitude of phase truncation spurs. Again, trust me, the computations get quickly out of hand. Especially for DDSs with large accumulators -- like our 48-b parts. Even for 32-b devices, the computations are cumbersome.

Your last statement sums things up nicely. The number of spurs can be as large as 2^N, where N is the accumulator size in bits. For a 32-b device, that's over 4 billion spurs -- significant processing and significant memory requirements.

"Is there a table where one can easily see the width (in bits) of the look-up-table for the various DDS chips? Wouldn't it be good to include such a column in the selection table / parametric search?"

I think this part has not yet been answered.

Here is a handy table giving the truncated phase word size plus other useful features found in our DDS products.

PDF

Thank you very much! That's indeed a really nice table.

Is there any new chip planned with a higher truncated phase word size? Maybe like 22 Bit? I know we are talking about a lot more memory making the chip much larger, but being able to avoid truncation spurs would be a really good thing.

Are you familiar with high speed DAC also? I thought about taking a FPGA with huge memory capacity, enough for a 22 bit phase to amplitude converter, and then feeding the amplitude output to a DAC.

You have quite a few DAC with output rates of 500MHz and above, but I have trouble finding phase noise data for them, while you have such data for most of your DDS chips.

Do you happen to have an according nice table for me as well?

P.S.:
The above table would still be nicer if it had two further columns with flicker and floor phase noise data. I know that this depends on the output frequency, but floor phase noise could be given where the noise really bottoms out (at some point lower output frequency does not further lower the phase noise floor) and flicker could be given normalized to at 1Hz offset and 1MHz output frequency (take typical value from datasheet graph, add 10 dB per decade that the offset frequency is above 1 Hz and substract 6dB for every factor of 2 the output frequency is higher than 1MHz).

Thank you very much! That's indeed a really nice table.

Is there any new chip planned with a higher truncated phase word size? Maybe like 22 Bit? I know we are talking about a lot more memory making the chip much larger, but being able to avoid truncation spurs would be a really good thing.

Are you familiar with high speed DAC also? I thought about taking a FPGA with huge memory capacity, enough for a 22 bit phase to amplitude converter, and then feeding the amplitude output to a DAC.

You have quite a few DAC with output rates of 500MHz and above, but I have trouble finding phase noise data for them, while you have such data for most of your DDS chips.

Do you happen to have an according nice table for me as well?

P.S.:
The above table would still be nicer if it had two further columns with flicker and floor phase noise data. I know that this depends on the output frequency, but floor phase noise could be given where the noise really bottoms out (at some point lower output frequency does not further lower the phase noise floor) and flicker could be given normalized to at 1Hz offset and 1MHz output frequency (take typical value from datasheet graph, add 10 dB per decade that the offset frequency is above 1 Hz and substract 6dB for every factor of 2 the output frequency is higher than 1MHz).

No, there are no short-term plans for a new DDS with higher phase truncation.

Actually, there is little to gain by having a truncation depth of more than 3 bits beyond the number of DAC bits. For example, a 10b DAC requires no more than 13b of phase resolution to ensure the generation of a sinusoid with 1/2 LSB amplitude resolution. Anything more that 1/2 LSB resolution yields marginal spurious improvement. Note that most of our DDSs employ at least 3 extra phase bits relative to the number of DAC bits.

Interestingly, the weakest link in the chain with regard to spurious is the DAC itself. In fact, DAC harmonics are typically the largest spurious constituent (magnitude) that appear as phase truncation spurs. To be clear, given a perfect DAC (no harmonic distortion at all), the largest phase truncation spur is approximately 3 - 6P (dBc), where P is the phase truncation depth in bits. So, a DDS that truncates phase at 15b (that is, 15 MSBs of phase), will exhibit phase truncation spurs of -87dBc max. However, the presence of DAC harmonics typically results in truncation spurs in excess of the theoretical maximum.

Like DDS, High-Speed DACs is its own product line. I'm not sure, but there may be a dedicated forum  on Eng'g Zone for DACs.

Your assumptions regarding only marginal improvement of decreasing phase truncation spurs further or eliminating them entirely may be valid if one just views the spur free dynamic range over a very wide range of frequencies.

But, often times one needs a much higher SFDR, but only within a limited frequency range. With careful frequency planning this can be achieved, but the higher the required SFDR is and the wider the according frequency range, the harder it is to find an appropriate frequency plan, especially if there are not only the harmonically related DAC quantization spurs but also some truncation spurs, which are even more difficult to predict.

Being able to avoid phase truncation spurs is a huge advantage in such applications, while it is very disappointing to find out that you cannot use the IC that would fit perfectly if the size of the truncated phase word was just one or two bits more.