On p. 6 in the datasheet of AD9915, in "Serial Port Timing" one can read
SCLK 80 MHz
SDIO to SCLK Setup Time 4.9 ns
SDIO to SCLK Hold Time 0 ns
SCLK Falling Edge to Valid Data on SDIO/SDO 78 ns
When the SCLK period is 12.5 ns, how is it possible to read data from the SPI port?
As there is no timing diagram, similar to Fig. 47, it is not clear what else can be the definition of the
"SCLK Falling Edge to Valid Data on SDIO/SDO" parameter.
Apparently, the data sheet fails to mention that serial port read operations are not guaranteed at 80MHz. Depending on supply voltage and silicon process parameters (fast vs. slow silicon), some devices cannot support read rates at 80MHz. Hence, the 78ns valid data spec. Read operations will require a reduction in the SCLK rate in order to guarantee valid data transfer.