We use the AD5598 for our VNA (Vector Network Analyzer) to measure the phase of the returned signal on a transmission line. CH0 is used as the output signal to the load, CH1 is compared with the reflected one. The idea was, to delay the phase of CH1 so, that it matches with that of the reflected signal. The phase for CH1 is then the phase delay of the transmission line.
CH0 and CH1 are set to the same frequency in a single ton mode ( let say to 14.00 MHz), CPOW0 for CH0 is set to 0x00 and for CH1 to 0x1000 (for 90°) according to the protocol on page 36 of the AD5598 manual.
After issuing an I/O Update to the chip, the frequency changes to the correct value, the phase difference between the two outputs is a random value!
Seting Bit 13 in FR2 (All channels autoclear phase accumulator) didn't change the channel behavior. Setting Bit 2 in the corresponding CFR registers of the channels didn't solved the problem either.
The AD5598 works in a single ton mode; we have now two wire communication with the chip. Data to the chip were verified with a logic analyzer, the phase control words correspond to our design (i.e. 0 and 0x1000). Changing the CPOW0 data f.e. for channel 1 successively from the initial value of 0x1000 to 0x1100 does not results in a linear phase shift, the phase of CH1 jumps randomly.
Where do we make the mistake, why does the phase shift not work? If necessary, I can provide you our code to initialize and to control the chip as well as the circuit diagram.