AD9910 Eval board issues?

The EVB software should install/operate properly with Windows 7. I suspect a setup issue of some sort.

Thanks Ken.

I have reinstalled it. I have the older version 1.0 of the software.  Even after reinsatllation the output is the same.

I tried to install the new version 2.1.0; but with this, the software doesn't even detect the Eval board and AD9910.

Any hardware settings issue could be suspected? or any thing to convey what could be problem.

The waveforms are so unstable and i can't monitor them on the scope for a measurement.

Thanks.!

Hi Shane,

Thanks for your help.

Now the software can read the Eval board and this is what I get as below: The USBEVBDPRG helped and now the EEPROM is read identical to the program.

However, the problem that I was facing in the first place has not been solved as yet i.e there is a heavily distorted waveform at the output at J4. My suspicions of new OS or outdated software has been

While it responds to the frequency changes at say profile 0 but the waveform itself appears like a FM waveform. Also the quality of the sine is distorted.

Any clues ? Any setting issues??

Are you using the device's internal system clock PLL?

What are you using for an input clock source?

Can you can post a screen shot of the output signal?

No Ken, I am using the option of the Crystal Oscillator located at the backside of the board.

Also the PLL is populated as follows: C15 =0.33nF, C13= 2.2nF and R37= 640 ohm. ( removed C51 & C52 and shorted R4 and R11)

The software is operated mostly in the default mode. The 'Enable Multiplier' option is not ticked. The freq is selected by double clicking on the profile 0 and then 'Loading'.

Below is 1Mhz generated by the board

Below is 10MHz generated

Below is 500Khz

Below is 30Mhz

Above is a screen shot of the software above  (I  know it is blurred ....sorry I don't know how to copy it better than the above) to give you an idea...

I'm a bit surprised you have any signal at all! Using the crystal requires the use of the internal system clock PLL (see the Clock Input section of the data sheet).

The best sanity check for making sure the DDS is alive is to measure the SYNC_CLK output (J9). But make sure the Enable I/O SYNC CLK Output Pin box is checked. Otherwise, the SYNC_CLK output driver is disabled yielding no signal at the SYNC_CLK pin. The SYNC_CLK signal is a direct divide-by-4 of the internal system clock. This gives you an easy way to verify the frequency of the internal system clock.

What is the SYNC_CLK frequency?

For getting started, I would recommend using a direct frequency source (e.g., an RF signal generator) as the REFCLK source rather than the crystal resonator (because using the crystal resonator forces you to use the PLL). But that means removing R4 & R11 and reinstalling C51 & C52. If you do use a direct source, be sure to check the /2 Divider Disable box. Otherwise, the system clock frequency will be 1/2 of what you expect.

Thanks Ken.  I am attaching the SYNC_CLK signal as captured on my scope.

This image is not stable as you can see. Frequency as measured is about  43 MHz

The below thing is the same waveform but with  STOP mode

If I have to feed external REF source,  then what should be the freq and voltage/amplitude levels?

Also, is there something wrong with the PLL components?

SYNC_CLK @ 40MHz implies a system clock frequency of ~160MHz. The excessive jitter tells me it is probably a parasitic oscillation due to an improperly configured device.

It is unlikely the exteranal PLL components are at fault.

To drive REFCLK from an external generator, connect a 50Ω source to J1 with a signal level of 1 to 2 Vpp. The frequency can be anywhere from 60MHz to 1GHz (your choice depending on your desired output frequency range).

However, since you already have the board configured to use the crystal, why not try the PLL? Check the Enable Multiplier box and set the Multiplier to 40. The PLL Lock icon should go green almost immediately, indicating that the PLL is up and running. These setting should yield a system clock frequency of 1GHz (40 x 25MHz = 1GHz).

Check the SYNC_CLK pin to verify all is well. You should see a 250MHz clock signal.

Hi Ken,

I sent an reply yesterday but seems to have lost somewhere.

Anyways, this is what I did. As suggested by you, using the on board crystal Iam able to get a clean signal at the output J4 with the following settings:

Enabled Multiplier-> Multiplier setting to 30- >System Clock @ 750MHz-> External clock set at 25MHz (default is 100MHz) In the above settings the PLL lock green icon is lit up.

However if I try to select the output frequency beyond 100MHz , the PLL lock green icon goes 'blank' and then the signal also goes jittery and untunable. I

Is there anything further I should try to set? or am I doing something wrong?

Here is  a snapshot of the signals:

10MHz signal

50MHz signal

Also, If I increase the multiplier to 31 and above the PLL goes out of 'lock'. Any reason why?

Always check the frequency of SYNC_CLK (Fsync) to make sure it indicates the expected system clock frequency (Fs), where Fs=4*Fsync.

Using the PLL requires selecting the appropriate VCO band based on the expected system clock frequency (see the "CLOCK INPUT" section of the data sheet for details on the VCO band selection). It is possible that increasing the multiplier to 31 put the expected system clock frequency beyond the range of the selected VCO band.

Changing the output frequency to 100MHz should have no impact on the operation of the PLL. That one's a mystery.

Hi Shane,

I have the same problem as Pra-kash. But, this link is not working for me (ftp://ftp.analog.com/pub/css/resource/vaf/AD9910_Evbd_Programmer.zip). Can yo please send me this simplified EvalBoard programmer.

Thanks,

Vijay

Hi Shane,

I have the same problem as Pra-kash. But, this link is not working for me (ftp://ftp.analog.com/pub/css/resource/vaf/AD9910_Evbd_Programmer.zip). Can yo please send me this simplified EvalBoard programmer.

Thanks,

Vijay