AD9913 no output


unfortunately I see no output on my DDS Chip.

I am using a single-ended source (Page 18. Figure 28 the last circuit) with 25MHz . When I measure the CLK right after the 0.1uF C there is a certain DC offset (1,2V), is that correct? With the intern PLL it should be 250MHz, that is the frequency the DDS needs?!


[edited by: DWeil346 at 5:23 PM (GMT 0) on 12 Aug 2019]
  • Possible problems with your code...

    CFR1[1]= 0b00001000;           //[31:24]  ==> [27]=1, which selects Internal Profile operation

    CFR1[2]= 0b00001000;           //[23:16] ==> [22:20]=0, which selects PROFILE 0 (because [27]=1)

    CFR2[2]= 0b00000010;      //[7:0] ==> [7:5]=0 selects DIFF clock input mode (this is why you see a DC bias); [4]=0 selects >5MHz input clock operation (correct assuming a 25MHz input); [3]=0 bypasses the input divider (this is OK); [2]=0 selects low frequency VCO (<100MHz); [1]=1 resets the PLL (not OK); [0]=X (read-only)

    CFR2[1]= 0b00010100;      //[15:8] ==> Set the PLL feedback divider to 10 (OK)

    uint8_t FTW [5]; ==> The FTW is not functional when using Internal Profile operation.

    Try this...

    CFR1[1] = 0x00 ([31:24]) ==> [27]=0 disables Internal Profile operation

    CFR2[2] = 0x84 ([7:0]) ==> [7]=1 selects CMOS clock input mode; [2]=1 selects high frequency VCO (>100MHz)

    Note that disabling Internal Profile operation should make the FTW register functional (as long as the device is in Single-Tone mode).