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# Problem in measuring impedance at lower frequency from 10 Hz to 1k Hz using AD5933

Hello everyone, I am developing an impedance measurement system using AD5933 with a microcontroller. I can measure impedance from 47 ohms to several mega ohms from frequency range 5k to 100k Hz. Now I want to measure impedance from frequency range 10 Hz to 4k Hz. I have uploaded my AFE picture. I know there are many threads related to lower frequency excitation, I have gone through them but I did not get an appropriate idea.

I have uploaded a picture below. According to my understanding after going through this table, we can measure impedance at a low-frequencies by simply giving an external clock to AD5933 pin. I have tried but it's just working for 16Mhz and 4Mhz external oscillator clock. For lower frequencies from 10Hz to 1K Hz how can we measure impedance, do we need any calculation for settling cycle register?

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• Quite an elaborate AFE you got there... The suspect would be the circuit R8R9R10C3 that acts as a low-pass filter with a time constant (R8||R9||R10)*C3 = 1.41630901288kOhm*1μF = 1.4 ms, so operating frequencies lower than a few KHz start noticeably leaking through. The suggestion would be to increase the resistors R8, R9, R10 (and, of course, R13 to keep R13/R10 ratio the same) or C3 or all the above. And prepare for long sweep duration.

If your current number of settling cycles works for your measurements at high MCLK, there should be not need to change it at lower MCLK.

• Thank you for your reply, I got this circuit from chabowski paper [1],  In this paper page num. 16 it is discussed that (ICA and ICB are for DC bias canceller. the voltage detectors are averaged on R8 and R9 and its correspond to DC bias voltage.

I think it's not an AFE problem because now I am trying to measure lower frequencies without AFE. I have measured 20kohm resistor with RFB 10kohm, it gives correct measurement from frequency sweep (5k-100k) by using 16Mhz external clock (settling cycle 0x64) and from 1khz to 5khz by using the 4Mhz external clock (settling cycle=0x0F), but when I am connecting 2Mhz external clock it acts as I have shown in video (running infinitely). but if I change the settling cycle from 0x0x0F to 0x05 it gives the result that I have shown in the image (not correct), I have measured 20kohm with 10kohm RFB.

1SIMPLE WIDE FREQUENCY RANGE IMPEDANCE METER BASED ON AD5933 INTEGRATED CIRCUIT

Konrad Chabowski, Tomasz Piasecki, Andrzej Dzierka, Karol Nitsch

Metrology & Measurement System, Vol. XXII (2015), No. 1, pp. 13–24.

• I have tried with Arduino UNO with 50kHz i2c frequency, but I am facing the same problem.

• AFAIK with Wire library you can go as low as 31KHz if you call Wire.setClock(31000L) after Wire.begin(). Maybe that would resolve your operation issues at low MCLK.

• Snorlax, I think I am doing some mistake in my code, I saw the post as you mentioned above, can you please tell what is L in the picture below that must be an integer as gennyelectro said, I am using the function for frequency code I mentioned below

```byte getFrequency(float freq, int n){
long val = long((freq/(MCLK/4)) * pow(2,27));
byte code;

switch (n) {
case 1:
code = (val & 0xFF0000) >> 0x10;
break;

case 2:
code = (val & 0x00FF00) >> 0x08;
break;

case 3:
code = (val & 0x0000FF);
break;

default:
code = 0;
}

return code;
}```

• Your function should work just fine as long as you change your global MCLK value in accordance with the clock frequency you feed the AD5933 chip.
As to the "L" gennyelectro discussed - it is the integer number of full cycles encompassed by the 1024-long sampled sequence to eliminate the effects of the DFT artifacts. Not sure if it is directly related to your problem.

• sorry for the late reply. I have solved my problem, Actually i was not waiting between reads.

• Great, best of luck with the rest of your endeavor!

• Hi   and  , may I know if you have added any additional circuitry between Out1 (DS1077L-66) and MCLK (AD5933). I have tried to generate 2MHz using DS1077L-40. I notice that the overshoots on the rising and falling edges of the clock waveform are very high. I have checked the generated waveform using an oscilloscope. The max and min voltage of the clock waveform are 6.72V and -1.68V respectively as shown in the picture below, which is way beyond the absolute maximum rating indicated in the datasheet (-0.3V to Vdd+0.3V).

I have added a 500pF shunt capacitor to filter out the spikes to ensure the waveform is within the absolute maximum rating as shown in the attached picture below. However, it seems like my AD5933 IC cannot detect the clock signal as my calibration keeps failing (calibration works on evaluation board with signal generator using the same source code, so it is definitely not the coding problem).

• Not sure I can be of help without seeing the setup. The AD5933 in my experience worked fine with just about any source of MCLK from general-purpose lab generators to chip oscillators of various kinds including programmable ones, just not the the DS1077L-40 specifically. Whenever chip oscillators were used they shared power supply with the AD5933, so the levels were automatically within working range. Also the wires/traces between the oscillator output and the MCLK input were typically under 10cm in length, so excessive over/undershoots were never observed.
How do you conclude that the calibration is failing? Does the problem occur when the output signal from the DS1077L-40 is fed to the evaluation board? If so, would it be possible to supply power to the DS1077L-40 from the evaluation board so that it would be the same as the AD5933 receives?
500 pF is probably too much, the DS1077L-40 datasheet seems to suggest that 50pF is the max load. To reduce the spikes while preserving reasonably sharp transitions people tend to use 10-30Ω resistors between the oscillator output and MCLK input.

• Hi  , thanks for replying. Please see below for the schematic of my setup:

I have posted my question in  Using DS1077L as External Clock for AD5933 MCLK as well. More pictures of waveforms from DS1077L-40 for different frequencies before and after filtering using a shunt capacitor can be found in this post. Would really appreciate if you could give me some comments over there.

Actually DS1077L has been used quite commonly for AD5933 IC. Basically I have not seen anyone who has added any external circuitry/filter between the MCLK and OUT1. Besides, as my DS1077L-40 is powered using STM32 Blue Pill 3.3V pin, I really have no clue why the overshoot spike can go up to 6.72V. As you mentioned about the wires/trace length, I am thinking if it is possible that the spikes are due to the probe connecting the DS1077L-40 and oscilloscope as the probe is more than 10cm? (I have set 10x on both the probe and oscilloscope as the bandwidth of 1x is too low so the overshoot cannot be detected.)

Regarding the calibration fail, I am using the AD5933 library from https://github.com/mjmeli/arduino-ad5933 , where there is a if-case that determines if the calibration is successful or failed.

I haven't tried to feed the output signal from DS1077L-40 directly to the EVAL-AD5933EBZ evaluation board yet. Will try and update here. Regarding if it is possible to power up DS1077L-40 using the evaluation board, I will try to short the 3 pins on LK6 (Datasheet pg39) and output the 3.3V to the DS1077L-40 via VDD-EXT on J2. Will update soon regarding this. Thank you for your suggestion.

Regarding the 50 pF max load, I believe what it means on the datasheet is the combined capacitive effect on the output pin instead of the maximum capacitance allowed to be connected externally at the output. Please see the link below for more info (although crystal oscillator is used as the example (Ctrl F: "Understanding Load Capacitance")):-

Moreover, thanks for recommending the 10-33ohm resistor. I have connected a 10ohm resistor onto the route between OUT1 and MCLK along with the shunt capacitor, which forms a low pass filter with cutoff frequency of 31.83MHz. The rising edge and falling edge of the waveform looks even better now. I am still trying out with different values of shunt capacitor. Will update some pictures here soon as well. Unfortunately, the calibration fail problem still persists. Is there any chance that my MCLK pin had been damaged so that it could not detect any external signal?

Apologies for the long reply. Would really appreciate if you could give me any suggestion for debugging please. Thanks in advance.

.

• Per your schematic both AD5933 and the  DS1077L-40 are powered from the same 3.3V source coming from the STM32, so there should be no issues with the clock and no need for any additional elements between the OUT1 and MCLK. It looks like the chps are physically close to each other, which makes your scope probe a suspect. Assuming the probe is properly compensated and the ground trace on your board between the chips is of a very low inductance, perhaps it has too long a ground wire to the alligator clip contacting the ground of your circuit. You might consider using spring-loaded ground pin instead.
Still it does not explain the software reporting failing calibration. The suspect would be the high value - 10uF - of the capacitor at Vout causing long transition, which the software in the library does not take into account. I would try making this capacitor about the same as on evaluation board, generate typical excitation frequency and see if the failure goes away.

• Per your schematic both AD5933 and the  DS1077L-40 are powered from the same 3.3V source coming from the STM32, so there should be no issues with the clock and no need for any additional elements between the OUT1 and MCLK. It looks like the chps are physically close to each other, which makes your scope probe a suspect. Assuming the probe is properly compensated and the ground trace on your board between the chips is of a very low inductance, perhaps it has too long a ground wire to the alligator clip contacting the ground of your circuit. You might consider using spring-loaded ground pin instead.
Still it does not explain the software reporting failing calibration. The suspect would be the high value - 10uF - of the capacitor at Vout causing long transition, which the software in the library does not take into account. I would try making this capacitor about the same as on evaluation board, generate typical excitation frequency and see if the failure goes away.

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• Hi  , I had tried to power up the DS1077L-40 using the 3.3V source on the EVAL-AD5933EBZ (via LK6) and connect it to the MLCK pin (via LK4) with and without the RC filter. My system did not respond at all when the RC filter was placed between MCLK and OUT1. Fortunately, after removing the RC filter and connect OUT1 directly to MCLK, the system works although the results are not perfect as shown below:

Hence, since the system works without filter, I believe that the overshoot spike is most likely due to the probe as you advised. However, I do not have any cable with the spring-loaded ground pin with me at the moment so I can't really dig further into this. No matter how, since the DS1077L-40 is working now, although it only works with the evaluation board currently, I will proceed to try with the AD5933 IC and my designed AFE and update again.

Regarding the 10uF capacitor, I do not think it is an issue. The reason I chose 10uF is to ensure that the cutoff frequency is lower than 1Hz (Freq_cutoff=1/(10uF||25kohm)=0.637Hz). I remember that I saw someone chose this value in some other posts in the forum as well. Besides, the calibration has no problem when I used the internal clock to sweep from 5kHz to 10kHz so I think the calibration fail is most likely due to the RC filter again. Will try and update soon.

Thank you so much for your help. I really appreciate it.

*Btw, I wonder how you are going add a 10uF capacitor on the evaluation board? I thought there is already a 47nF capacitor on the board? Sorry for my silly question.

• My system did not respond at all when the RC filter was placed between MCLK and OUT1.

Yes, to be expected, as most digital systems require sharp transitions at the front and trailing edges of the clock meander. Whenever you have spikes at the edges, more often than not there is some parasitic inductance involved in the sircuit, primary suspect would be the ground lead on the scope probe, less likely inductance of the wire carrying the clock signal, even less likely the inductance of power and ground traces (usually taken care of by the power bypassing capacitors, which you do have in your circuit). So, the MCLK signal is not likely the issue, no need to worry about amending the scope probe, etc. Perhaps using clock signal without any filteris should be fine.

Regarding the 10uF capacitor, I do not think it is an issue.

If the software did not report calibration failure when the chip was running on the internal oscillator then it is not an issue. Just for the future consideration, the low cut-off frequency comes at a price of a lengthy transition when the INITIALIZE WITH START FREQUENCY COMMAND takes the chip out of standby mode, see Figure 28. Frequency Sweep Flow Chart on p.22 of the datasheet. On the diagram it says: "AFTER A SUFFICIENT AMOUNT OF SETTLING TIME HAS ELAPSED...", but the third-party software you are using might not be waiting long enough when this capacitor is much larger than the one assumed by the software developer. With 10 uF the software should wait 5-7 sec for the circuit to reasonably settle.

Btw, I wonder how you are going add a 10uF capacitor on the evaluation board?

Could be a bit challenging if you do not have soldering/repair equipment for SMD components. The easiest thing would be to add whatever capacitor you need in parallel to C7 on the board by soldering the leads to the exposed pins using a very small soldering iron tip. Alternatively, perhaps you can find a ceramic 10uF SMD capacitor of the same footprint as C7 and glue its pads on top of the corresponding C7 pads using conductive adhesive (aka Silver Adhesive, etc.). Will require steady hands and sharp eyes or/and a decent magnifying glass.

although the results are not perfect as shown below

I think your setup is functional and what you see is the result of the chip introducing its own, the so-called "system phase" into the measurements. It is possible to account for it and other potential issues through proper calibration. Can help you with that once you have settled with the hardware.