I am designing some equipment for eddy current testing. The AD5934 and AD5933 seem to be a good choice to simply the impedance measurement section of the design. However I find the data sheets are unclear. As far as I can tell the two chips are basically the same except for the A/D sampling rate (also the temp measurement and internal clock on the AD5933) However both data sheets say the conversion time is about 1 mS with a 16 MHz clock. See page 22 under "NUMBER OF SETTLING TIME CYCLES " in the AD5934 data sheet. Is this an error? Should the conversion take about 4 mS with the AD5934?
I think this approximation of 1 ms for the conversion process using 16.777 MHz clock was derived on this computation. The ADC performs the conversion of n-bit every T=1/16.777MHz which is approximately 60us, Thus a 12-bit conversion takes at least 12 clock cycles that is 12*60us=720us. There is also some overhead for some tasks from the conversion around 4 additional clock cycles that is 4*60us=240us. Adding up the two values gives around 1ms of conversion time.
I do not quite get your calculation.
T=1/16.777 MHz = 5.96E-8 s
Which is 0.06 µs, not 60 µs. A 12-bit conversion would therefore take 12*0.06 µs = 0.72 µs. So it would all add up to ~ 1µs, not 1 ms.
Can you explain further? I was currently reading up on the NUMER OF SETTLING TIME CYCLES REGISTER part of the data sheet as well. The documentation seems to be a bit confusing.
Can someone from AD make a statement on the calculations behind the settling time cycles?
Apologies for the off units. You are right that the computation would give 60ns and not 60us. As for the settling time cycle, I think this thread might help https://ez.analog.com/dds/f/q-a/29347/ad5933-can-settling-time-cycles-register-value-be-0
thanks for your reply. I have read the entire thread, but is does not seem like there was any solution. Is there no document that can fully describe the settling time cycles register? The thread you sent me was from 2014 and people still do not quite understand it correctly, i think.
Thanks anyways and best regards,
Unfortunately, page 15 and 25 of the AD5933 data sheet is the only document that describes the settling time cycles.