Direct Digital Synthesis (DDS)

Q&A

by Carter-Huang
Direct Digital Synthesis (DDS)

Latest 1 day ago by Jules.Nikko
66 1 0
Not Answered
AD9958 Can't output WAVES 0
Not Answered

Hi： My customer use Xilinx FPGA control AD9958, i had checked the SCH, also SPI communicate is OK, LOOP filter connect to AVDD, Clock_Mode_sel GND, using 25Mhz extrnal CLK, CLK PLL gain 20 to 500Mhz internal, can get 125Mhz clk in SYNC_CLK . So I think...

software clock and timing Direct Digital Synthesis (DDS) ad9958

66 1 0
by TakeC
Direct Digital Synthesis (DDS)

Started 1 day ago
11 0 0
Not Answered
How to restart the DRG sweep signal using only GPIO 0
Not Answered

When issuing a DRG sweep signal with the AD9910 DDS in the ascending direction only, with No-dwell-high on and No-dwell-low off, is there a way to restart from the initial frequency after reaching the upper frequency limit using only GPIO? Initially,...

Datasheet/Specs clock and timing Direct Digital Synthesis (DDS) ad9910

11 0 0
by Sarmad
Direct Digital Synthesis (DDS)

Latest 6 days ago by Sarmad
109 2 0
Not Answered
AD9910 Output Impedance 0
Not Answered

I am driving 50 ohms load using one of the outputs of AD9910. I measured S11 at this output using a VNA and got this response, i.e. output is mismatched from 185 MHz to 305 MHz. This is a custom DDS board that was procured from third party. Each of...

hardware clock and timing impedance matching Direct Digital Synthesis (DDS) output impedance ad9910 Show More

109 2 0
by embedd
Direct Digital Synthesis (DDS)

Latest 15 days ago by embedd
336 6 0
Answered
cannot get output signal +1
Answered

Hi, I am using stm32g4 with AD9951 (I am using 400Mhz crystal), I can read and write back all the registers correctly, correctly disable and enable the SYNC_CLK, and measure it to be exact 100MHz (400MHz/4). The problem I am having is I cannot get any...

ad9951 hardware clock and timing no output Direct Digital Synthesis (DDS) Show More

336 6 0
by hamzatamer
Direct Digital Synthesis (DDS)

Latest 15 days ago by hamzatamer
105 2 0
Answered
AD9959 SYNC CLK doesn't work. 0
Answered

Hello, I am attempting to control the AD9959 Evaluation Board using an external microcontroller via SPI. My goal is to achieve a SYSCLK of 500 MHz (PLL x20 on a 25 MHz Ref_Clk). The primary issue is that the SYNC_CLK signal does not initialize or start...

sync_clk Datasheet/Specs spi clock and timing clk ad9959 Direct Digital Synthesis (DDS) ad9959 eval io_update Show More

105 2 0
by AishwaryaKV
Direct Digital Synthesis (DDS)

Latest 19 days ago by AishwaryaKV
181 3 0
Not Answered
Amplitude Modulation using AD9910 0
Not Answered

I am trying to generate an Amplitude Modulated signal using RAM method AD9910 Eval board . Here is the setting. I am using a .txt file that was already provided with GUI to generate an envelope. But the interesting part is nothing is getting generated...

AD9910 EVAL hardware clock and timing Direct Digital Synthesis (DDS) ad9910 Show More

181 3 0
by fussylogia
Direct Digital Synthesis (DDS)

Latest 23 days ago by fussylogia
102 2 0
Not Answered
125MHz spur 0
Not Answered

Hi, I have been using AD9912 for my clocking needs for a long while. Recently i realized that there is a 125MHz spur in some of pins. For example near the status pins, this spur is very observable. Sysclk is 1GHz and output frequency is around 120Mhz...

hardware clock and timing ad9912 Direct Digital Synthesis (DDS)

102 2 0
by onyuhara
Direct Digital Synthesis (DDS)

Latest 23 days ago by onyuhara
94 2 0
Not Answered
Creating Fixed/Variable Phase Offset Between Two AD9914 DDS Chips 0
Not Answered

Hello everyone, I am working on a project that requires generating two synchronized RF signals with a precise, controllable phase difference using two AD9914 DDS chips. My Goal: To synthesize a single frequency signal (e.g., f_out ) using two AD9914...

hardware clock and timing Direct Digital Synthesis (DDS) ad9914

94 2 0
by shiba183
Direct Digital Synthesis (DDS)

Latest 24 days ago by shiba183
164 2 0
Answered
Data latency 0
Answered

Hello, My customer had chosen AD9914. Regarding the Frequency in Sweep Mode (Match Latency Disabled), can I understand this value as the time from when I/O UPDATE is input until the waveform actually changes? Currently, customer intends to set...

Datasheet/Specs hardware clock and timing Direct Digital Synthesis (DDS) ad9914 Show More

164 2 0
by Longnb4
Direct Digital Synthesis (DDS)

Latest 27 days ago by Jules.Nikko
125 1 0
Answered
Support Request: AD9914 Output Instability Observed on 3 out of 50 Units +1
Answered

Dear Analog Devices Support Team, I hope this message finds you well. We are currently in mass production of a module that uses the AD9914 to generate an LO signal around 1 GHz . During production testing, 3 out of 50 boards have shown abnormal output...

hardware clock and timing Direct Digital Synthesis (DDS) ad9914

125 1 0
by Rahulreddy
Direct Digital Synthesis (DDS)

Latest 1 month ago by AlexAtienza
110 1 0
Not Answered
undefined 0
Not Answered

Why the SCLK is going low (gradually decreasing) after 2ms till it reaches zero?

hardware Quadrature Digital Up Converters (QDUC) High Speed D/A Converters =30MSPS ad9957

110 1 0
by medo
Direct Digital Synthesis (DDS)

Latest 1 month ago by furkanc696
417 5 0
Not Answered
NO output and SPI connection problem for AD9958 0
Not Answered

Hello I have designed a PCB with AD9958 and using “530AC125M000DG “ as a LVPECL Differential Clock Oscillator. here you can find the Schematic connection of Si530 oscillator as per "www.micro-semiconductor.cz/.../81-SI5XX5X7-EVB.pdf" and next...

c software SPI connection clock and timing dds Direct Digital Synthesis (DDS) ad9958 Show More

417 5 0
by sincplicity
Direct Digital Synthesis (DDS)

Latest 1 month ago by Jules.Nikko
182 3 0
Not Answered
Looking for Example on doing a FMCW using the RAM? 0
Not Answered

I would like to use the RAM on the AD9910 to do an FMCW Chirp from 100-150MHz with a constant phase offset and dwell in-between successive chirp. It's not clear to me how to setup the RAM for this operations. Could someone provide and example or explain...

hardware clock and timing fmcw dds Direct Digital Synthesis (DDS) ad9910 Show More

182 3 0
by AnkurEmbedded
Direct Digital Synthesis (DDS)

Started 1 month ago
85 0 0
Not Answered
EIS 12V 17AH VRLA BATTERY 0
Not Answered

Dear All, I have following 12v 18ah vrla battery. AD5933 Evalution kit. Target : Electrochemical Impedance Spectroscopy I AD5933 acceptance is 5v, so i m using 12v-5v voltage converter here. Rest for EIS what additional interfacing i needed. Kindly...

hardware clock and timing Direct Digital Synthesis (DDS) ad5933

85 0 0
by onyuhara
Direct Digital Synthesis (DDS)

Latest 1 month ago by onyuhara
193 3 0
Not Answered
About Reference CLK input impedance 0
Not Answered

Hello everyone, I'm working on a board design and need expert advice on the termination and AC coupling for a differential reference clock (REF_CLK) input to AD9914. The clock frequency is approximately 3.8 GHz. Here is the current circuit configuration...

hardware clock and timing Direct Digital Synthesis (DDS) ad9914

193 3 0

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Q&A

Not Answered
AD9958 Can't output WAVES 0
Not Answered

Not Answered
How to restart the DRG sweep signal using only GPIO 0
Not Answered

Not Answered
AD9910 Output Impedance 0
Not Answered

Answered
cannot get output signal +1
Answered

Answered
AD9959 SYNC CLK doesn't work. 0
Answered

Not Answered
Amplitude Modulation using AD9910 0
Not Answered

Not Answered
125MHz spur 0
Not Answered

Not Answered
Creating Fixed/Variable Phase Offset Between Two AD9914 DDS Chips 0
Not Answered

Answered
Data latency 0
Answered

Answered
Support Request: AD9914 Output Instability Observed on 3 out of 50 Units +1
Answered

Not Answered
undefined 0
Not Answered

Not Answered
NO output and SPI connection problem for AD9958 0
Not Answered

Not Answered
Looking for Example on doing a FMCW using the RAM? 0
Not Answered

Not Answered
EIS 12V 17AH VRLA BATTERY 0
Not Answered

Not Answered
About Reference CLK input impedance 0
Not Answered

Q&A

Not Answered AD9958 Can't output WAVES 0 Not Answered

Not Answered How to restart the DRG sweep signal using only GPIO 0 Not Answered

Not Answered AD9910 Output Impedance 0 Not Answered

Answered cannot get output signal +1 Answered

Answered AD9959 SYNC CLK doesn't work. 0 Answered

Not Answered Amplitude Modulation using AD9910 0 Not Answered

Not Answered 125MHz spur 0 Not Answered

Not Answered Creating Fixed/Variable Phase Offset Between Two AD9914 DDS Chips 0 Not Answered

Answered Data latency 0 Answered

Answered Support Request: AD9914 Output Instability Observed on 3 out of 50 Units +1 Answered

Not Answered undefined 0 Not Answered

Not Answered NO output and SPI connection problem for AD9958 0 Not Answered

Not Answered Looking for Example on doing a FMCW using the RAM? 0 Not Answered

Not Answered EIS 12V 17AH VRLA BATTERY 0 Not Answered

Not Answered About Reference CLK input impedance 0 Not Answered

Not Answered
AD9958 Can't output WAVES 0
Not Answered

Not Answered
How to restart the DRG sweep signal using only GPIO 0
Not Answered

Not Answered
AD9910 Output Impedance 0
Not Answered

Answered
cannot get output signal +1
Answered

Answered
AD9959 SYNC CLK doesn't work. 0
Answered

Not Answered
Amplitude Modulation using AD9910 0
Not Answered

Not Answered
125MHz spur 0
Not Answered

Not Answered
Creating Fixed/Variable Phase Offset Between Two AD9914 DDS Chips 0
Not Answered

Answered
Data latency 0
Answered

Answered
Support Request: AD9914 Output Instability Observed on 3 out of 50 Units +1
Answered

Not Answered
undefined 0
Not Answered

Not Answered
NO output and SPI connection problem for AD9958 0
Not Answered

Not Answered
Looking for Example on doing a FMCW using the RAM? 0
Not Answered

Not Answered
EIS 12V 17AH VRLA BATTERY 0
Not Answered

Not Answered
About Reference CLK input impedance 0
Not Answered