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AD9102/AD9106 DDS Programming Questions

I have selected the AD9106 for inclusion into a piece of commercial test equipment I’ve designed.  I have the Eval board (AD9102-ARDZ & the EVAL-SDP matching processor) and have been working with them. I have it doing most of what I desire.  However, I have a few issues (see below) that I could use some explanations.   


What I’m trying to do:

  • I need to make a 0-10khz two carrier frequency (FSK) modulated waveform.  That is, small one carrier for a time, followed by a second of a different frequency then repeat forever.  An additional catch is that the two frequencies are of differing amplitudes.    An example plot is referenced for a basic two-tone FSK, but no mention as to how.  (See Figure 53, of the AD9102 datasheet). Again note: In my case, the two carriers need to be of different amplitudes.
    • Related: The datasheet states: “When the frequency of the DDS needs to change within each pattern period, a sequence of values stored in SRAM is combined with a selection of DDSTW_MSB bits to form a tuning word.”   Explain?  I assume this is somehow tied to CMD Reg 0x47.  But the datasheet offers little on what the meaning of bits [4:0] imply?  Or, how to use them.

  • Is there a way to get DOUT to pulse after each pattern period?  It seems to imply that it only outputs on a pre/post delay of Trigger#. Not all that useful for my application.

  • What is the difference between Digital Gain (Cmd Addr 0x32-0x35) , and Analog Gain control  (Cmd Address 0x4-0x7)? Digital seems to be working for me but only provides a 0-1V output range. (into 100ohm current shunt)

  • A DDS source can be amplitude modulated (Figure 52-Chirp). Can Tuning Words in memory be mixed with modulation waveforms? For example, First Carrier for a time, modulated in SRAM, followed by Frequency two, also followed by AM modulation in SRAM all inside a single pattern period?


For reference, I’m using an external 8Mhz clock source and the Internal amplifiers turned on.

Inquiring minds want to know

D. Aldrich

UTE Inc. 

Added plot.
[edited by: UTE at 7:46 PM (GMT -4) on 3 Aug 2021]
  • Hello ,

    It's nice to know that you are using the board we released earlier this year and that it is working. Grin

    About your questions, please see my initial responses below. Will try to add more details later.

    1. I think storing pattern data in SRAM is best for your application. Please see Q10 in this document: ad910x faqs
        About your follow-up question, here is a related thread where example files for a frequency modulated waveform is uploaded: ad9106-sine-output-and-tuning-words. Unfortunately, amplitude is uniform all throughout.

    2. You are correct on DOUT function.

    3. Digital gain is applied on the DAC output path while analog gain is for full scale current scaling and calibration. Although digital gain range is -2 to +2, DAC output will be clipped at the max/min output compliance voltage.

    4. Again, please see Q10 in this document: ad910x faqs