AD9914 - Digital ramp duration is not fixed over a whole time range

Hello,

We are using an AD9914 with Digital Ramp generation and we have noticed that the high ramp duration is not fixed to for a whole amount of time. Instead, lower ramp don't suffer this issue.

Concretely, starting the DRG at t = 0, the first high ramp duration is always longer than the rest of the ramps, and starting from the second high ramp, the duration has a logarithmic grown.

The DRG is configured with both no-dwell bits high.

Each ramp duration is measured with an FPGA.

Follows are some ramp duration measurements for 4 captures of consecutives DRG sequences, in therms of clock cycles @12MHz (so 12500 clock cycles duration = approx 1.04 ms), where each capture corresponds to approx. 30 seconds:

The current register map programmed to the DDS is the following:

0x00 00 01 20 08 
0x01 00 0E 29 00 
0x02 00 04 19 0C 
0x03 00 05 21 20 
0x04 5E B8 51 EB 
0x05 73 33 33 33 
0x06 00 00 0C E2 
0x07 14 7A E1 47 
0x08 04 11 00 01 
0x09 00 00 00 00 
0x0A 00 00 00 00 
0x0B 00 00 00 00 
0x0C 00 00 00 00 
0x0D 00 00 00 00 
0x0E 00 00 00 00 
0x0F 00 00 00 00 
0x10 00 00 00 00 
0x11 00 00 00 00 
0x12 00 00 00 00 
0x13 00 00 00 00 
0x14 00 00 00 00 
0x15 00 00 00 00 
0x16 00 00 00 00 
0x17 00 00 00 00 
0x18 00 00 00 00 
0x19 00 00 00 00 
0x1A 00 00 00 00 
0x1B 00 00 08 00

Does someone have an idea about why the high ramp duration is not fixed starting from the first ones.

Thanks.

s.