Hi every one.
We are using AD9914 with direct ref. clock at 3.0GHz. Most of the time it is working well, but....
We discover a trouble about sync_clk output, the phase of this signal change time to time.
I also capture another effect, most of time, this signal is referred from GND with 33% ratio, but sometime, this signal become and stay inverted, referred from 3.3v !! See attached picture.
The rising/falling time of "sync_clk" is partially limited by my oscilloscope, but i am convinced it is also limited by AD9914 itself.
In any case, is someone understand why "sync_clk" change its phase ?
Why "sync_clk" become inverted and referred to +3.3V ?
I have to say our schematic about ref. clock design is exactly the same as AD9914 evaluation board !
Thank's for help.
The AD9914 has SYNC_CLK invert bit on CFR2.
I tried it using the evaluation board and software and got the same behavior that you are getting.
SYNC_CLK invert bit = 0
SYNC_CLK invert = 1
I think you are accidentally toggling the SYNC_CLK invert bit in programming your AD9914.
thank's for your contribution.
I think you are right, now I am also convinced this bit is set, but the only thing we do with our specific board+FPGA is to write FTW in direct mode (Function pins = "0000"). I suppose we have a wrong timing about Func[3:0] + Data[31:0] that can cause this effect. We will see around this way.
I have a second remark, there is a difference between your and mine chronograph, in normal case "sync_clk" not inverted, in my case, there is a short rising edge and a long falling edge, but in your case, you have a long rising edge and a short falling edge. Maybe it is just a video effect due to my old oscilloscope + probe. I will re-do measure with a better instrument.