Recently, I use a Xilinx FPGA(Spartan6-lx9tqg144) to control the ad9910. I let the AD9910 work in the DRG mode, and I got the DRG mode work, realizing the freqency sweep from 200MHz to 250MHz.
furthermore, I wanna to get the following waves, but I do not know how to make it.
Let Ti(i=1,2,3,4,5...) denote the time duration
T1 : 0-1us , AD9910 output a 200MHz sinusodial waveT2 : 1-10us, AD9910 output noneT3 : 10-11us, AD9910 output a 200MHz sinusodial waveT4 : 11-20us, AD9910 output noneT5 : 20-21us, AD9910 output a 202MHz sinusodial waveT6 : 21-30us, AD9910 output noneT7 : 30-31us, AD9910 output a 202MHz sinusodial waveT8 : 31-40us, AD9910 output none......The process may repeat from 200, 202, ... 249, to 250 MHz
(1) I found that, the maxium speed of the Serial Port of AD9910 is 70Mbps. that means, in 1us, 70bits are transmited at the most. If I use the ASF Register to control the Amplitude, I should send8+32 bits(Phase One 8bits, and Phase two 32bits) via the SPI protocolDoes it mean that it is hard for us to update the registers in 1us?
(2) If I use the parallel data mode, Can I make it?
(3)And I found that,If I use the ADI's AD8180(a multiplex chip, which has a 5ns channel switch time), Maybe I can control the output, but I am not so sure.
Because, I currently use the prototype board, I wanna to know How to use the AD9910 to Control the output amplitude?
Any advise are appreciated.Thank you
No, I suggest using one of the single-tone profiles to control the DDS output frequency, not the DRG.
CFR1=1 enables the OSK functionality. Table 5 indicates that the amplitude source is the ASF register is when manual OSK is in effect and that the ASF register has the highest priority of any other amplitude source (except for the OSK generator, but that is only effective for auto OSK mode).
NOTE: You will need to provide a connection from your FPGA to the OSK pin for this to work.
Execute the loop below for all desired frequencies. The loop generates a 1us tone, 9us quiet, 1us tone, 9us quiet for each frequency.