how to let ad9910 output a train of  pulsed sinusodial waves

Hi, everyone.

Recently, I use a Xilinx FPGA(Spartan6-lx9tqg144) to control the ad9910. I let the AD9910 work in the DRG mode, and I got the DRG mode work, realizing the freqency sweep from 200MHz to 250MHz.

furthermore, I wanna to get the following waves, but I do not know how to make it.

Let Ti(i=1,2,3,4,5...) denote the time duration

T1 :  0-1us , AD9910 output a  200MHz sinusodial wave
T2 :  1-10us, AD9910 output none
T3 :  10-11us, AD9910 output a 200MHz sinusodial wave
T4 :  11-20us, AD9910 output none
T5 :  20-21us, AD9910 output a 202MHz sinusodial wave
T6 :  21-30us, AD9910 output none
T7 :  30-31us, AD9910 output a 202MHz sinusodial wave
T8 :  31-40us, AD9910 output none
......
The process may repeat from 200, 202, ... 249, to  250 MHz

(1) I found that, the maxium speed of the Serial Port of AD9910 is 70Mbps. that means, in 1us, 70bits are transmited at the most.
If I use the ASF Register to control the Amplitude, I should send
8+32 bits(Phase One 8bits, and Phase two 32bits) via the SPI protocol
Does it  mean that it is hard for us to update the registers in 1us?

(2) If I use the parallel data mode, Can I make it?

(3)And I found that,
If I use the ADI's AD8180(a multiplex chip, which has a 5ns channel switch time), Maybe I can control the output, but I am not so sure.

Because, I currently use the prototype board, I wanna to know How to use the AD9910 to Control the output amplitude?


Any advise are appreciated.
Thank you

JiongWU

Parents
  • No, I suggest using one of the single-tone profiles to control the DDS output frequency, not the DRG.

    CFR1[9]=1 enables the OSK functionality. Table 5 indicates that the amplitude source is the ASF register is when manual OSK is in effect and that the ASF register has the highest priority of any other amplitude source (except for the OSK generator, but that is only effective for auto OSK mode).

    NOTE: You will need to provide a connection from your FPGA to the OSK pin for this to work.

    SET UP:

    1. Write CFR1[9]=1 (enable OSK).
    2. Write all 1's to the ASF register (full scale amplitude).
    3. Choose a single-tone profile (Profile 0, for example). You will use Profile 0's 32-bit FTW register for changing the frequency every 20us (see OPERATION below).
    4. Set OSK pin to Logic 0 (amplitude OFF).
    5. Program Profile 0 FTW for 200MHz and issue an IO_Update (frequency is active, but output is OFF).

    OPERATION:

    Execute the loop below for all desired frequencies. The loop generates a 1us tone, 9us quiet, 1us tone, 9us quiet for each frequency.

    Loop

    1. Set OSK pin to Logic 1 (amplitude ON) and start 1us timer.
    2. Wait for 1us timer to expire, then set OSK pin to Logic 0 (amplitude OFF) and start 9us timer.
    3. Program Profile 0 FTW register for next frequency via SPI. NOTE 1 -- This does not cause a frequency change until you issue an IO_Update. NOTE 2 -- You should have no trouble writing this 32-bit register within the following 9us time window.
    4. Wait for 9us timer to expire, then set OSK pin to Logic 1 (amplitude ON) and start 1us timer.
    5. Wait for 1us timer to expire, then set OSK pin to Logic 0 (amplitude OFF), start 9us timer and issue IO_Update (previously written FTW becomes active, but no output because amplitude is OFF).
    6. Wait for 9us timer to expire.

    Repeat

Reply
  • No, I suggest using one of the single-tone profiles to control the DDS output frequency, not the DRG.

    CFR1[9]=1 enables the OSK functionality. Table 5 indicates that the amplitude source is the ASF register is when manual OSK is in effect and that the ASF register has the highest priority of any other amplitude source (except for the OSK generator, but that is only effective for auto OSK mode).

    NOTE: You will need to provide a connection from your FPGA to the OSK pin for this to work.

    SET UP:

    1. Write CFR1[9]=1 (enable OSK).
    2. Write all 1's to the ASF register (full scale amplitude).
    3. Choose a single-tone profile (Profile 0, for example). You will use Profile 0's 32-bit FTW register for changing the frequency every 20us (see OPERATION below).
    4. Set OSK pin to Logic 0 (amplitude OFF).
    5. Program Profile 0 FTW for 200MHz and issue an IO_Update (frequency is active, but output is OFF).

    OPERATION:

    Execute the loop below for all desired frequencies. The loop generates a 1us tone, 9us quiet, 1us tone, 9us quiet for each frequency.

    Loop

    1. Set OSK pin to Logic 1 (amplitude ON) and start 1us timer.
    2. Wait for 1us timer to expire, then set OSK pin to Logic 0 (amplitude OFF) and start 9us timer.
    3. Program Profile 0 FTW register for next frequency via SPI. NOTE 1 -- This does not cause a frequency change until you issue an IO_Update. NOTE 2 -- You should have no trouble writing this 32-bit register within the following 9us time window.
    4. Wait for 9us timer to expire, then set OSK pin to Logic 1 (amplitude ON) and start 1us timer.
    5. Wait for 1us timer to expire, then set OSK pin to Logic 0 (amplitude OFF), start 9us timer and issue IO_Update (previously written FTW becomes active, but no output because amplitude is OFF).
    6. Wait for 9us timer to expire.

    Repeat

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