how to let ad9910 output a train of  pulsed sinusodial waves

Hi, everyone.

Recently, I use a Xilinx FPGA(Spartan6-lx9tqg144) to control the ad9910. I let the AD9910 work in the DRG mode, and I got the DRG mode work, realizing the freqency sweep from 200MHz to 250MHz.

furthermore, I wanna to get the following waves, but I do not know how to make it.

Let Ti(i=1,2,3,4,5...) denote the time duration

T1 :  0-1us , AD9910 output a  200MHz sinusodial wave
T2 :  1-10us, AD9910 output none
T3 :  10-11us, AD9910 output a 200MHz sinusodial wave
T4 :  11-20us, AD9910 output none
T5 :  20-21us, AD9910 output a 202MHz sinusodial wave
T6 :  21-30us, AD9910 output none
T7 :  30-31us, AD9910 output a 202MHz sinusodial wave
T8 :  31-40us, AD9910 output none
......
The process may repeat from 200, 202, ... 249, to  250 MHz

(1) I found that, the maxium speed of the Serial Port of AD9910 is 70Mbps. that means, in 1us, 70bits are transmited at the most.
If I use the ASF Register to control the Amplitude, I should send
8+32 bits(Phase One 8bits, and Phase two 32bits) via the SPI protocol
Does it  mean that it is hard for us to update the registers in 1us?

(2) If I use the parallel data mode, Can I make it?

(3)And I found that,
If I use the ADI's AD8180(a multiplex chip, which has a 5ns channel switch time), Maybe I can control the output, but I am not so sure.

Because, I currently use the prototype board, I wanna to know How to use the AD9910 to Control the output amplitude?


Any advise are appreciated.
Thank you

JiongWU

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  • Hi Kenny,

    Thank you for your fast reply.

    I write down the operations to see if I got your ideal

    Step 1.  Let the AD9910 Work in the DRG mode. Set the ASF Register to Ful Scale.

    Step 2.  Every 20us, I write  to the Digital Ramp Limit Register(0x0B), to set the Upper Limit and The Lower Limit the same Frequency Word, e.g. 200MHz , 202MHz or  the other number.

    But the Digtal Ramp Limit Register is a 64 Bits Register. What you say is  32Bits.  I guess Maybe it is wrong.

    Maybe  Let the AD9910 work in the Single Tone Mode. But When I refer to the AD9910's datasheet,  I found that

    in the Page 21, table 5 Data Source Priority. Only the RAM mode or DRG mode correspond  to the OSK enabled conditon. And I get confused about it.

    JiongWU

Reply
  • Hi Kenny,

    Thank you for your fast reply.

    I write down the operations to see if I got your ideal

    Step 1.  Let the AD9910 Work in the DRG mode. Set the ASF Register to Ful Scale.

    Step 2.  Every 20us, I write  to the Digital Ramp Limit Register(0x0B), to set the Upper Limit and The Lower Limit the same Frequency Word, e.g. 200MHz , 202MHz or  the other number.

    But the Digtal Ramp Limit Register is a 64 Bits Register. What you say is  32Bits.  I guess Maybe it is wrong.

    Maybe  Let the AD9910 work in the Single Tone Mode. But When I refer to the AD9910's datasheet,  I found that

    in the Page 21, table 5 Data Source Priority. Only the RAM mode or DRG mode correspond  to the OSK enabled conditon. And I get confused about it.

    JiongWU

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