Re: AD9959 Synchronizing Master and Slave

Hi Mark,

I have one more question regarding AD9959.

We are using two AD9959 chips in our design and wanted to control one as master and one slave and sync their clocks. To demonstrate this, I have setup with two AD9959 Eval boards, sync out of master is connected to sync in of slave.

I am using Ref clock: 50MHz and multiplier: 8, so system clock is 400MHz and Sync clock is 100MHz. Output frequency is 4MHz to 14MHz.

From AD9959 datasheet, I understand in order to synchronize  (using manual software mode synchronization) both the sync clocks we need to load bit FR1[0] or check the box in Multi device sync box and click on load.

When both sync clocks are in phase but I don’t see output clocks are in synchronization, I have to go through this process for a while, for example, for 4MHz output frequency I need to go for 20 times in order to synchronize both output and sync clocks of master and slave. This is not feasible in real-time application.

For some frequencies, it is harder to synchronize output frequencies as well as sync clocks of master and slave. Is there a better way to synchronize both sync clocks and output frequencies. By the way automatic mode synchronization does not work,  I do not why.

I am happy to provide more information on this issue if you need.

Below is setting of master eval board.

Thanks

Uma

attachments.zip
  • I am able to figure out this by following certain sequence of powering on and configuring slave and master and also by checking auto clear phase accumulator, but i have seen another issue.

    I am getting both master and slave sync clocks and output waveforms are in sync, but once in a while output waveforms are out of phase by 1 sync clock ( Tperiod:10ns). I have captured the waveforms in oscilloscope and observed that master IO update (both master and receives same IO update, but probed in master eval and slave eval) violating setup time (4.8ns), it is around 4.44ns. This is happening once in 30 IO updates, but this is cause of concern for us as we dont know when it happens and it can causes error in the system.

    From the datasheet i understand that we can send the IO update synchronously with sync clock (so far i am sending IO update asynchronously), i would like to know more information on this and also i would like to know how to implement this in the eval boards. 

    Waveform details:

    Yellow Trace : Slave Sync (100 MHz)

    Sky blue Trace : Slave IO Update

    Purple Trace: Master Sync (100 MHz)

    Green Trace : Master IO Update

    Thanks

    Uma