AD9834: Operation of DDS

Question When I have 10 Mhz master clock and I want to have 1 Mhz output frequency, how many points (time domain) will my output signal have? Answer The tuning word specifies the output frequency as a fraction of the reference clk frequency, therefore a tuning word representing fout =1Mhz, with a system clk of 10Mhz, will be represented digitally as 1/10. The phase accumulator is actually a modulus M counter that increments its stored number each time it receives a clock pulse, therefore when you generate a 1Mhz o/p using s system clk of 10Mhz, you will have 10 o/p sample points in your o/p signal.

AD9834: MSB output jitter reduction

Question We would like to get a output square wave by using of AD9834. The MSB is output at pin 16 but the edge is jittering and the waveforms have been attached. As we know, the jitter of output is dominated by that of MCLK, but the problem is still exists when the jitter of MCLK is less. Could you please tell us how to decrease the jitter and what performance we can achieve? Answer We did some analysis on this with the AD9834 and a 5th order elliptic filter. We filtered the Iout signal and fed it back into the Vin pin. The Comparator was enabled and fed back out on the Sign Bit Out pin. The jitter reduce from the inverse of the MCLK (13nS) to ~600pS. Further filtering would improve this. This was for a 10MHz signal with a 40MHz LP filter – so if we moved the corner frequency down to say 12 MHz we would achieve better jitter still.

14-bit DDS to Output Triangle Waveformt at speeds >75MHz

Question Do you have a 14-bit DDS chip with Triangle Output, faster than 75MHz. Answer Unfortunately our series of DDS Waveform Generator parts are limited to 10-bits of resolution. Only certain DDS parts can switch between a sine-wave, triangle-wave, or a square wave output. These parts are the AD9833/AD9834 and AD5930/AD5932. The highest operating frequency of these parts is the A9834 at 75MHz. However, it seems some of our higher speed DDS parts (>75MSps) like the AD9910/AD9911 can be modified to output triangle outputs, please see the following thread on Engineer Zone (post by DSB): http://ez.analog.com/message/23245#23245 It is recommended to get an evaluation board to evaluate this capability. Note, in this mode the max effective DAC sample rate is the SYNC_CLK rate or 1/4th the system clock rate. The reason, the sweep circuitry is clocked at the SYNC_CLK rate not the system clock. So, the input sample rate to the DAC input (to form a triangle waveform via Sweeper) equals the SYNC_CLK * x where x ranges from ( 1 to 2^16). X represents the Digital ramp rate register 0x0D. This this will produce a sampled triangle waveform, if it is required to filter this sampled waveform it could distort the waveform at the filtered output.