Clarification on AD7403 Datasheet’s Clock Edge Instructions

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The AD7403 Rev. B datasheet suggests reading data on the positive clock edge and mentions data access time after the MCLKIN rising edge (pages 5 and 19). However, the code on page 19 uses “always @ (negedge mclk1, posedge reset)”, indicating that the accumulator and input are sampled on the negative edge. This is not a mistake. The reason for the negative edge mclk1 being there is to ensure that the data is read on the successive (the very next) rising edge. The first rising edge is where the sigma-delta modulator is accessed. Here, posedge reset is nothing but the second rising edge. (see the figure below).

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