Question
We found that the output frequency is not stable and the integrator output is like a saw tooth wave.I have checked the VFC function mentioned in the datasheet. It seems that the saw tooth wave can not be avoided and the output frequency will have anoccasional change (one clock period) unless the input current (voltage) can be exactly divided by the reference current (voltage) and outputfrequency is exactly derived from the clock.
We are confused that if the charge balance can not be precisely achieved, would the output frequency be unstable?Could we use the SVFC part for a steady clock divider?It seems continuous frequency change could not be realized when input voltage or current continuously changes.How could we define the linearity under this circumstance?
Answer
The pulses in the output are related to the master clock. If the output frequency is equal to MCLK/4, MCLK/8, etc, then an output pulse stream offixed frequency is generated. With the output frequency is equal to MCLK/4, there is a pulse generated at the output every 4 MCLK cycles. If theoutput data rate equals MCLK/8, there is a pulse generated at FOUT every 8 MCLK cycles.If the output frequency is some other value, the VFC cannot generate pulses at the fixed rate. The customer needs to look at the pulses generatedover a period of time to determine the output frequency. So, the customer can use the VFC for any frequency. However, they need to count the pulsesover a period of time to calculate the frequency. This is always the case when the output pulses are related to the MCLK.
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