ADG3308: Design queries

Question We try to use the AG3308 as Level Translator between a 3.3V-FPGA with IP-Core for MC68HC11A1 and diverse 5V-I/Os at our different applications. Now there are some questions upcoming reading the datasheet. 1. Input Driving: We measured switching at an input current of about 2mA, required as in datasheet are 36mA. 2. How is DataDirection at PowerUp? 3. Can I use an input in parallel with an ADC-Input? ... and some more questions in future? Answer Question 1; This looks correct. But the architecture of the input requires the one Shot detects a rising edge, and turns on the PMOS transistor for a short period of time. To ensure this for all inputs, 36mA may be required. Question 2; With Vccy required to be powered up first, and also the EN pin being driven from Vccy, then this is the default power up. But ,once both power supplies are up , the device can be driven in either direction. Question. 3; I am not too sure about the third question. it would be best to buffer the ADC. Any switching noise on the ADG3308 will inherently effect the performance of the ADC. Buffereing the ADC will reduce switching noise on the ADC.

ADG3308 bidirectional, setting the direction

Question I am going to use the ADG3308 for level translation between 2.5 and 5V logic. I see that there is no direction pin. Can individual bits go in one direction and the other the opposite? Or do all the bits have to be going in the same direction? Answer The ADG3308 is bidirectional and doesn't need any logic signal to set the direction. One channel only will transmit in one direction at a given moment of time. By applying a signal at A you will get the level translated signal at the other end, Y. The same applies if you do it the other way round, Y to A.

ADG3308 and indeterminate i/p o/p state's interface query

Question not sure what happens if both the input and output are in indeterminate states. can you advise Answer We advise and use the En pin as the control to disable the ADG during FPGA interafce startup. or use a pull-up on either side of the ADG to maintain logic level at one side.