Working at 8KHz sample rate

Question Here a customer would like to use 8KSPS sample rate of AD1974. I have sent the configuration to him as you suggested before. However, they also would like the part working at 48KSPS as well. That means, they need 2 crystals in the board. Now they have designed the board, they asked if they can use the part in slave mode and provide the required sample clock on ALRCLK and use ALRCLK as the PLL input. Then they do not need to put another crystal on the board. Answer The AD1974 PLL will not lock to an Fs below 32 kHz; the part MUST be run in direct mode. For this application, they are correct that 2 MCLK sources are necessary. I would recommend that they use 512 x Fs mode when the using Direct Lock. It would be easiest if they left the PLL off for both modes and switched only the MCLK frequencies to change modes. I would recommend that they mute the ADCs during the switch using ADCC0 [5:2]. To save power, they can set PLLCC0 [0] = 1 For 512 x Fs PLLCC0 [2:1] = 10 So PLLCC0 = 0x85 They will need a 4.096 MHz and a 24.576 MHz clock. They should set PLLCC1 as follows: PLLCC1 [1:0] = 11 So that PLLCC1 = 0x03 To mute the ADC: ADCC0 = 0x3C

I2S interface configuration

Question In AD1974 datasheet, it mentions AD1974 can support right justified, left justified, I2S and TDM mode. But there is no register descriptions on how to enable right justified and left justified? Answer The BCLK delay register for ADC and DAC should be set according to the customers needs: 0 BCLK delay = LJ 1 BCLK delay = I2S 8 BCLK delay = RJ for 24-bit audio in 32 BCLK frame 12 BCLK delay = RJ for 20-bit audio in 32 BCLK frame 16 BCLK delay = RJ for 16-bit audio in 32 BCLK frame TDM mode supports I2S and LJ modes only.

AD1974 Stop Band Filter Response

Question What is ADC Stop-Band Filter Response @96kHz and @192kHz of AD1974? Answer The AD1974 ADC Stop Band and Pass Band frequencies scale linearly with Fs, according to the multiplier in the datasheet, Table 6. This holds true across the entire range of sample rates, up to the 192 kHz upper limit. @96KHz: Stop Band Frequency = 0.5625 * 96KHz = 54KHz @192KHz: Stop Band Frequency = 0.5625 * 192KHz = 108KHz

Unused analog input pin connection

Question My signal is single ended signal, how do I connect the negative analog input pin. Answer The ADC and DAC pins of a Sigma Delta analog port have Common Mode voltage. These pins should never be tied directly to GND; increased current consumption and reduced performance will result. In the case where a single ended source is the only option, the unused ADC pins should be AC coupled to GND, not tied directly.