Hardware:
- Connect 120kΩ resistor from ISET to GNDF
- Connect IFET to GNDF
- Connect 10nF capacitor from GATE to GNDF
Initialization Values:
MAX14001_write(MAX14001_WVR_adr, 0x294);
MAX14001_write(MAX14001_FLTEN_adr, 0x7e); // disable MVL and FET
MAX14001_write(MAX14001_CFG_adr, 0x0c); // Set filter to x8
MAX14001_write(0x10 + MAX14001_WVR_adr, 0x294); // write verification register
MAX14001_write(0x10 + MAX14001_FLTEN_adr, 0x7e); // write verification register
MAX14001_write(0x10 + MAX14001_CFG_adr, 0x0c); // write verification register
ADC Read Command:
MAX14001_read(MAX14001_ADC_adr);
Register Definitions:
/* Register_Name Direction */
/*---------------------------------------------*/
#define MAX14001_ADC_adr = 0x00; /* ADC R/W */
#define MAX14001_FADC_adr = 0x01; /* Filtered ADC R/W */
#define MAX14001_FLAGS_adr = 0x02; /* Error Flags R/W */
#define MAX14001_FLTEN_adr = 0x03; /* FAULT Enable R/W */
#define MAX14001_THL_adr = 0x04; /* Lower Threshold R/W */
#define MAX14001_THU_adr = 0x05; /* Upper Threshold R/W */
#define MAX14001_INRR_adr = 0x06; /* Inrush Reset R/W */
#define MAX14001_INRT_adr = 0x07; /* Inrush Trigger R/W */
#define MAX14001_INRP_adr = 0x08; /* Inrush Pulse R/W */
#define MAX14001_CFG_adr = 0x09; /* Configuration R/W */
#define MAX14001_ENBL_adr = 0x0a; /* Enable R/W */
#define MAX14001_WVR_adr = 0x0c; /* Write Verification R/W */
// verification registers
#define MAX14001_FLTV_adr = 0x13; /* FAULT Enable verification R/W */
#define MAX14001_THLV_adr = 0x14; /* Lower Threshold verification R/W */
#define MAX14001_THUV_adr = 0x15; /* Upper Threshold verification R/W */
#define MAX14001_INRRV_adr = 0x16; /* Inrush Reset verification R/W */
#define MAX14001_INRTV_adr = 0x17; /* Inrush Trigger verification R/W */
#define MAX14001_INRPV_adr = 0x18; /* Inrush Pulse verification R/W */
#define MAX14001_CFGV_adr = 0x19; /* Configuration verification R/W */
#define MAX14001_ENBLV_adr = 0x1a; /* Enable verification R/W */