Question:
For VL and Vcc, is there any special sequence (power-up and down) requirements
Answer:
No. For VL and VCC, there are not any special power up/down sequence requirements with regard to device damage.
Although not mentioned in the datasheet, the Abs Max Ratings for VL are the same as for VCC. The device won't be damaged by reversing VCC with respect to VL. However, when powering down VCC to 0V, while VL is still present all the IOVL_ pins will be strongly pulled up by an internal PFET connected between VL and IOVL_ whose Rdson is in the range of 10ohms. It is a very strong pullup that can generate troubles on IOVL_ lines. This pullup occurs regardless of the state of the /THREE STATE\ input pin.