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Precision DACs
Documents AD536x and AD537x: FAQs
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Precision DACs requires membership for participation - click to join
  • +Documents
  • FAQ: nanoDAC+ Family AD531x/AD568x/AD569x/AD567x
  • FAQs: DAC Daisy Chain
  • FAQs: DAC Communication Troubleshooting
  • FAQs: DAC Power-up sequence and Biasing
  • +AD420: FAQs
  • +AD421 data input interfacing with optocoupler
  • AD5024: Operating temperature of evaluation boards
  • AD5060 Ground Voltages
  • AD5065 t7 maximum timing
  • AD5111, AD5113, AD5115: Shutdown mode
  • AD5115 Digipot
  • AD5116: Pull-up / Pull-down resistors
  • AD5121: VDD and VLOGIC
  • AD5121: Maximum Bandwidth
  • AD5121: Maximum Current Density
  • AD5141: Operation below 2.3VDD
  • AD5141: Programmable LDO
  • AD5141: Power Supply Sequence
  • AD5142 - IBIS File
  • AD5161: Error in equation 4 / effect of wiper resistance, VW
  • AD5203: Negative voltage at the output
  • AD5206: Timing
  • AD5222: Absolute maximum ratings, latchup, zero code resistance and distortion
  • AD5222: Residual audio signal
  • AD5522: Bandwidth of the Signal that can be Measured by the Comparator
  • +AD5232: FAQs
  • AD5235: Daisy chain
  • AD5235: Programming
  • AD5243 VOL output logic level
  • AD5248 fuse bit / power up at midscale
  • +AD524: FAQs
  • AD5251, AD5252, Theta JC Values
  • AD5252 I2C pins on VDD+0.3V
  • AD5252: Channal matching
  • +AD5254 - different VDD and I2C bus voltage
  • AD5258 datasheet shows how to calculate RWA and RWB. These AD5258 data sheet  max Rwb query
  • AD5259 - "Not Connected Option - third logical stage "1", "0", "NC" ??
  • AD5259 I2C Device Address
  • What type of non-volatile memory hast the AD5270? What is its retention time?
  • AD5272_wiper resistance
  • AD5263, connection of Digital Pot SHDN Pin 15
  • AD527x resistance calculation
  • AD527x, how to measure the resistance value of digipot
  • AD5290: Nominal resistance
  • AD5290: Unused SDO output to tie or not to tie or leave it open that is the question
  • AD5292: SPI Mode issues
  • AD5293: shift register DIN with MSB first or least?
  • AD5301 Signal Accuracy and Absolute Error
  • AD5301: Reference usage
  • AD5318: locked status due to power on
  • AD5321_I2C level translator
  • AD5323: Thermal Analysis Data
  • AD5331: output voltage range and reduced output swing with greater loading
  • AD5338: Difference in offset between channel 1 and channel 2 of the AD5338
  • AD53500: Thermal questions
  • AD5363 AD5362_SPI communication with Blackfin processor
  • -AD536x and AD537x: FAQs
    • AD536: Using a potential divider
    • FAQ: Selecting A Reference for the AD536x and AD537x DACs
    • FAQ: How Does the PEC Function Work in AD536x DACs?
    • FAQ: Selecting An Output Range for the AD536x and AD537x DACs
    • FAQ: Using the Offset Register in AD536x and AD537x DACs
    • FAQ: X1A and X1B Registers in the AD536x and AD537x DACs
  • AD5370: Data Input Format
  • AD5383-5 maximum current that can be supplied by each voltage output?
  • AD5383: Pin connections
  • Using toggle mode in the AD5384 using an I2C interface
  • AD5405_four quadrant resistors
  • AD5412: Connect the AD5412/AD5422's Iout and Vout pins directly together
  • AD5412 output voltage range
  • AD5413 FAQ
  • +AD5420 using an external resistor RSET
  • AD5421: Intrinsic safety - voltage / capacitance minimizing
  • The AD5420/AD5422 does not seem to function as I expect when using external RSET?
  • AD5421 Supply Pin Configuration
  • AD5421 Si revisions and influence on HART tests
  • +AD5422 - Connecting multiple DVCC outputs together
  • AD5429: DAC not responding to sending of serial word
  • AD5439: crosstalk problem
  • AD5440 - Pin out query
  • AD5443: Using SYNC as a Chip Select Pin
  • AD5446: SFDR
  • AD5449 mixed mode DACloading query
  • AD5449: Output noise spectral density
  • AD548B replacement is ADA4062
  • AD549: Higher noise
  • AD549: Noise problem
  • +AD5522 Evaluation Board kit documenation does not match datasheet Rev E?
  • AD5544: Long term drift over time
  • AD5546: reference input circuit
  • AD5553 Operating Temperature
  • AD5554: Bias over temperature
  • AD5660: Can multiple AD5660 devices be updated simultaneously?
  • AD5664: Connection to the Exposed Pad of the Chip Scale Package for AD5664?
  • AD5554: Current circuit
  • Is AD5556 usable without negative voltage?
  • ad557: Maximum output current
  • AD5592R
  • AD5623R CLR pin
  • AD5627: LDC - Pin connections - continuos V out
  • AD5640: Increasing gain
  • AD565A: did a AD565A/BIN exist?
  • AD5662: Output Buffer does not reach the Rails at nanoDac and add additional FSR Erroro - related to ALL nano Dacs with Voltage Output Buffer
  • AD5668: Datasheet output noise, figures 45, 46 and 47 labelled incorrectly
  • AD5696R  I2C SDA stuck on GND
  • +AD5700 Protocols
  • AD5700/AD5700-1 & Full Duplex Operation
  • AD5722R, NC pins have 2 additional working DAC channel outputs (same as AD5724R)
  • Can you confirm 2's Complement coding in Table 14 of AD5724 datasheet Rev. D?
  • AD5724: Digi-POT_Bandwidth
  • AD574: Maximum ratings for 10V input
  • AD5750 hardware mode OUTEN
  • AD5750-1: Can the software determine which variant of AD5750 is populated -1 or -2?
  • +AD5755 Non-Linearity
  • AD5761/21/R FAQ
  • AD5764_SYNC pin as CS.
  • AD5780: Error 1172 (.NET exception) when starting AD5780 evaluation software
  • AD5791 daisy chain
  • AD5791 Noise?
  • AD5791 question re Gain of Two Configuration
  • AD5791: Recommended reference
  • ad667: If CS\=0 are input latches transparent
  • AD667: supply voltage
  • AD688_internal resistors value
  • +AD698: FAQs
  • AD694: Bandwidth of buffer and IC
  • AD8403: Connecting to digital
  • AD8842: Moulding compound
  • AD9913 interfacing circuit
  • ADG506ATE/883B operating temperature and thermal resistance in Leadless Ceramic Chip Carrier Package
  • Can DAC SPI pins be left floating for a while before the micro is configured
  • CN0336: Where can I find a solution for a receiver in a 4-20mA current loop sensor application?
  • DAC8800BR/883C datasheet
  • Daisy chaining AD5271 and ADG714 possibility
  • Daisy Chaining AD532x parts
  • Digital potentiometer: Rheostat mode:  Bandwidth calculation
  • Does AD5245 (Potentiometer) have a log or linear taper?
  • Error in Figure 32 - 2-wire serial bus
  • EVAL-AD5791SDZ for arbitrary function generators
  • Eval-ADUCM360QSPZ + Demo-AD5700D2Z
  • How often can I write to the AD5141's  internal EEPROM?
  • AD693: Is there an AD693 RoHS version?
  • Key differences in specification between the AD674BBD and BTD grades
  • nanoDAC+ family
  • schematic diagram to control AD9913
  • The maximum acceptable clock rise time for the AD5160's reliable operation?
  • Where can I find the tape width for a tape reel of devices ?
  • Which package device is populated on the AD5669RSDZ eval board?

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FAQ: Using the m and c Registers on AD536x and AD537x DACs

Q.

How do I use the m and c registers on AD536x and AD537x DACs?

----------------------------------------------------------------------

A.

The AD536x and AD537x have an m and a c register per channel. The m register controls the gain of the transfer function and the c register controls the offset of the channel. The default value for the m register is 0xFFFF for 16-bit resolution DACs and 0x3FFF for 14-bit resolution DACs. The default value for the c register is 32768 for 16-bit resolution DACs and 8192 for 14-bit resolution DACs.


When the m register is programmed with a value less than the maximum (i.e. the default value) the slope of the transfer function is decreased. For example, the default output span will be reduced by half if the m register is programmed to half its default value. Note that changing the value of the m register does not change the value of 1 LSB. If the m register is set to half it’s default value the output range is also set to half the nominal output range. In this case the user can still use the full range of the input register (X1A or X1B) but the output will still change in units of 1 LSB (of the default values).

The c register can be used to add or remove offset from a channel. Each LSB is the same size as that of the data register. Offset can only be removed when the value in the data registers (X1A or X1B) is greater than or equal to the amount of offset to be removed. For example, X1A=200 and c = default-10 is equivalent to X1A = 190 and c = default. Obviously, if X1A =20 and c = default – 50, the output will not be able to remove add this much negative offset and output will be capped at its minimum value.

General Information:

This document covers the denseDAC family. AD536x refers to the AD5360, AD5361, AD5362 and AD5363 eight and 16 channel DACs. AD537x refers to the AD5370, AD5371, AD5372 and AD5373 thirty two and 40 channel DACs.

 
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