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AD5065 t7 maximum timing

I'd like to have information about the maximum required timing on t7 on the
AD5065 datasheet. I don't understand why the SYNC signal should be brought to
high in less than 30ns. I don't understand why, and chiefly I'm not able to
manage this from my FPGA, running with a 20MHz clock (50ns step for the
management of my SPI -> 10 MHz SPI clock). This requirement is really
surprising, and I guess this would not be respected by most of the
microcontroller's integrated SPI peripherals.
So I need your help to make me understand if this timing is really required in
any case, or if it is required to cover, for instance, the protocol with a
50MHz SPI Clock, or in some particular case. Moreover, my SPI clock is not
activated during SYNC=1 so perhaps this
requirement is not applicable in this case ?


The t7 parameter max of 30ns is due to a digital bug. There is a workaround
where you can use a software LDAC to update the output. If you keep /LDAC high
and use command 0010 or 0011 (table 8) to update the DACs you don't need to
adhere to the 30ns spec.