idle. It needs to be held LOW! The datasheet (fig. 3 and 4) suggest, that it
can be either high or low, which is false!
The SCK line needs to be LOW IDLE. It CANNOT be held high!
1- The DS (figure 3 and 4) clearly states the SPI mode used in this part,
, in other words, when SYNC is pulled low, SCLK should be low. Timing diagram
shows the same,
2- Additionally, this part disables physically the digital input buffers (SCLK,
DIN) when SYNC is high, in other words, the level of SCLK is ignored, so not
sure why customer says that SCLK should be low during idle. This can be easily
checked in the part by measuring the digital feedthrough.
I believe the root cause of the problem is that customer didn’t use the
appropriate SPI mode.