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Precision DACs
Documents AD5331: output voltage range and reduced output swing with greater loading
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  • AD420: Accuracy of Vout
  • AD420: Maximum output current and maximum current absorption
  • AD420: Output voltage range
  • AD420_external current boost transistor
  • AD421 data input interfacing with optocoupler
  • AD5024: Operating temperature of evaluation boards
  • AD5060 Ground Voltages
  • AD5065 t7 maximum timing
  • AD5111, AD5113, AD5115: Shutdown mode
  • AD5115 Digipot
  • AD5142 - IBIS File
  • AD5161: Error in equation 4 / effect of wiper resistance, VW
  • AD5203: Negative voltage at the output
  • AD5206: Timing
  • AD5222: Absolute maximum ratings, latchup, zero code resistance and distortion
  • AD5222: Residual audio signal
  • AD5232 Daisy Cain Mode Issues
  • ad5232: Connection of VSS
  • AD5232: Daisy chain
  • AD5235: Daisy chain
  • AD5235: Programming
  • AD5243 VOL output logic level
  • AD5248 fuse bit / power up at midscale
  • AD524: Thermal resistance
  • AD524: Theta JA(Junction to Ambient Temperature) and Theta JC (Junction to case Temperature)
  • AD524: Working in a strong magnetic field
  • AD5251, AD5252, Theta JC Values
  • AD5252 I2C pins on VDD+0.3V
  • AD5252: Channal matching
  • AD5254 - different VDD and I2C bus voltage
  • AD5258 datasheet shows how to calculate RWA and RWB. These AD5258 data sheet  max Rwb query
  • AD5259 - "Not Connected Option - third logical stage "1", "0", "NC" ??
  • AD5259 I2C Device Address
  • AD5263, connection of Digital Pot SHDN Pin 15
  • AD5272_wiper resistance
  • AD527x resistance calculation
  • AD527x, how to measure the resistance value of digipot
  • AD5290: Nominal resistance
  • AD5292: SPI Mode issues
  • AD5293: shift register DIN with MSB first or least?
  • AD5301 Signal Accuracy and Absolute Error
  • AD5301: Reference usage
  • AD5318: locked status due to power on
  • AD5321_I2C level translator
  • AD5331: output voltage range and reduced output swing with greater loading
  • AD5338: Difference in offset between channel 1 and channel 2 of the AD5338
  • AD53500: Thermal questions
  • AD5363 AD5362_SPI communication with Blackfin processor
  • AD536: Using a potential divider
  • AD5370: Data Input Format
  • AD5383-5 maximum current that can be supplied by each voltage output?
  • AD5383: Pin connections
  • AD5405_four quadrant resistors
  • AD5412 output voltage range
  • AD5420 using an external resistor RSET
  • AD5420: ASYNCHRONOUS CLEAR Function
  • AD5420: fault flag state is indeterminate when digital power is applied first.
  • AD5420: What happens to output current if supply voltage drops below 10.8V, at what point is shutdown?
  • AD5421 Si revisions and influence on HART tests
  • AD5422 - Connecting multiple DVCC outputs together
  • AD5422: 3 pin SPI interface
  • AD5422: HART compatability
  • AD5422: What is the role of R27 Socket in AD5422's EVB?
  • AD5422_SPI daisy chain reading
  • AD5429: DAC not responding to sending of serial word
  • AD5439: crosstalk problem
  • AD5440 - Pin out query
  • AD5446: SFDR
  • AD5449 mixed mode DACloading query
  • AD5449: Output noise spectral density
  • AD548B replacement is ADA4062
  • AD549: Higher noise
  • AD549: Noise problem
  • AD5522 Evaluation Board kit documenation does not match datasheet Rev E?
  • AD5546: reference input circuit
  • AD5553 Operating Temperature
  • AD5554: Bias over temperature
  • AD5554: Current circuit
  • ad557: Maximum output current
  • AD5592R
  • AD5623R CLR pin
  • AD5640: Increasing gain
  • AD565A: did a AD565A/BIN exist?
  • AD5662: Output Buffer does not reach the Rails at nanoDac and add additional FSR Erroro - related to ALL nano Dacs with Voltage Output Buffer
  • AD5696R  I2C SDA stuck on GND
  • AD5700 logic signal isolation
  • AD5700 Protocols
  • AD5700: HART Manufacturing ID
  • AD5722R, NC pins have 2 additional working DAC channel outputs (same as AD5724R)
  • AD574: Maximum ratings for 10V input
  • AD5750 hardware mode OUTEN
  • AD5750-1: Can the software determine which variant of AD5750 is populated -1 or -2?
  • AD5755 Non-Linearity
  • AD5755_vsense connection_DCDC_transfer function
  • AD5761/21/R FAQ
  • AD5764_SYNC pin as CS.
  • AD5791 daisy chain
  • AD5791 Noise?
  • AD5791 question re Gain of Two Configuration
  • AD5791: Recommended reference
  • ad667: If CS\=0 are input latches transparent
  • AD667: supply voltage
  • AD688_internal resistors value
  • AD698 becoming hot
  • AD698 power supply current calculation
  • AD698 Supply Voltage versus Output Voltage
  • AD698: 6 wire sensor connection
  • AD698: Lead/lag pins
  • AD698: Maximum input at A and B input
  • AD698: phase lead / phase lag compensation
  • AD698: Power supply
  • AD698: Power supply +/-12V
  • AD698: R3 calculation error in datasheet phase lead phase lag compensation
  • AD8403: Connecting to digital
  • AD9913 interfacing circuit
  • ADG506ATE/883B operating temperature and thermal resistance in Leadless Ceramic Chip Carrier Package
  • Alternative FET recommendation for AD421
  • Bandwidth of buffer and IC
  • Bandwidth of the Singal  that can be Measured by the Comparator
  • Can DAC SPI pins be left floating for a while before the micro is configured
  • Can multiple AD5660 devices be updated simultaneously?
  • Can you confirm 2's Complement coding in Table 14 of AD5724 datasheet Rev. D?
  • CN0336: Where can I find a solution for a receiver in a 4-20mA current loop sensor application?
  • Connect the AD5412/AD5422's Iout and Vout pins directly together
  • connection to the Exposed Pad of the Chip Scale Package for AD5664?
  • Current loop and HART with 4 channels
  • DAC8800BR/883C datasheet
  • Daisy chaining AD5271 and ADG714 possibility
  • Daisy Chaining AD532x parts
  • Datasheet output noise, figures 45, 46 and 47 labelled incorrectly
  • DEMO-AD5700D2Z kit : Finding a low cost IDE
  • digi-POT_Bandwidth
  • Digital potentiometer: Rheostat mode:  Bandwidth calculation
  • Do the AD5254 adjustable resistors have galvanic isolation?
  • Does AD5245 (Potentiometer) have a log or linear taper?
  • Error in Figure 32 - 2-wire serial bus
  • EVAL-AD5791SDZ for arbitrary function generators
  • Eval-ADUCM360QSPZ + Demo-AD5700D2Z
  • FAQ: AD5421 Supply Pin Configuration
  • FAQ: AD5700/AD5700-1 & Full Duplex Operation
  • FAQ: How Does the PEC Function Work in AD536x DACs?
  • FAQ: Selecting A Reference for the AD536x and AD537x DACs
  • FAQ: Selecting An Output Range for the AD536x and AD537x DACs
  • FAQ: Using the m and c Registers on AD536x and AD537x DACs
  • FAQ: Using the Offset Register in AD536x and AD537x DACs
  • FAQ: X1A and X1B Registers in the AD536x and AD537x DACs
  • FAQs: DAC Communication Troubleshooting
  • FAQs: DAC Daisy Chain
  • FAQs: DAC Power-up sequence and Biasing
  • How often can I write to the AD5141's  internal EEPROM?
  • Intrinsic safety - voltage / capacitance minimizing
  • Is AD5556 usable without negative voltage?
  • Is there an AD693 RoHS version?
  • Key differences in specification between the AD674BBD and BTD grades
  • Labview Error 1172 (.NET exception) when starting AD5780 evaluation software
  • LDC - Pin connections - continuos V out
  • long term drift over time
  • Maximum Bandwidth
  • Maximum Current Density
  • Moulding compound
  • nanoDAC+ family
  • nanoDAC+ Family AD531x/AD568x/AD569x/AD567x FAQ
  • Offset Adjustment and Gain Adjustment
  • Operation below 2.3VDD
  • Power Supply Rails
  • Power Supply Sequence
  • PRECISION DAC SUPPORT COMMUNITY
  • Problem with HART Modem
  • Programmable LDO
  • Pull-up / Pull-down resistors
  • Purpose of the switch on the RTS - HART_OUT line
  • schematic diagram to control AD9913
  • Setting up the AD5755
  • The AD5420/AD5422 does not seem to function as I expect when using external RSET?
  • The maximum acceptable clock rise time for the AD5160's reliable operation?
  • Thermal Analysis Data
  • Thermal resistance value of AD5755
  • unused SDO output to tie or not to tie or leave it open that is the question
  • Using SYNC as a Chip Select Pin
  • Using the AD5755 family in Applications Without Dynamic Power Control
  • Using toggle mode in the AD5384 using an I2C interface
  • VDD and VLOGIC
  • What is the maximum junction temperature of AD698 or the maximum permissible power dissipation?
  • What type of non-volatile memory hast the AD5270? What is its retention time?
  • Where can I find the tape width for a tape reel of devices ?
  • Which package device is populated on the AD5669RSDZ eval board?

AD5331: output voltage range and reduced output swing with greater loading

Q 

Output voltage range and reduced output swing with greater loading
I am incorporating into a new design the above device. I have
a question on the sink/source capability of the device. Figure
15 of the datasheet shows the output changing with respect to
load, does this just occur near to the two supply rails or will
this occur througout the output voltage range? Or can we source/sink
current from any voltage within the lines on the graph without
the output changing?

 

A 

Looking at the way the AD5331 is specified, if you want to have the maximum
output range you should not load the output. Note that in the small print the
DC specifications are tested with the output unloaded while the remaining
specifications are tested with the output connected to ground via a 2k resistor.

The limitation here is the output buffer. An amplifier with a true rail to rail
output stage can swing to within  1mV of the rails if the output current is
less than 1uA. This matches with the AD5331 specifications. However, as soon as
any significant current is sunk or sourced from the amplifiers output, there is
a finite output resistance.

We are now going into the realm of rail to rail output op-amp territory rather
than strictly DAC technology, so please bear with me. What you have at the
output of the AD5331 is basically a rail to rail op-amp configured either as a
unity gain buffer or as a gain of 2 non-inverting amplifier.

When the output voltage is not near either rail, the negative feedback action
of the buffer maintains a very low output resistance. If extra current is
sourced or sunk from the output, the negative feedback loop simply re-adjusts
the drive to the output stage so that the extra current is supplied. Drawing
extra current (within limits) does not cause the output voltage to change
significantly. In this case 0.5 Ohms is the specification given for the AD5331
output impedance at DC.

However, when the output approaches the rails, the internal circuitry begins to
saturate and the FET in the output stage is turned fully on and just looks like
a resistance between the output and the supply rail. Since the FET has no "room
to move" and can't be forced more "on" than it already is, the negative
feedback action described above has no more scope to function and all you see
is a passive resistance to the rail. Drawing current through this resistance
results in a voltage drop across the resistance. You can calculate this output
resistance from figure 15:
R = V/I = 0.3V / 6mA = 50 Ohms.

So the question is:
At what output voltage does the negative feedback cease to be effective causing
the output resistance to rise?
The answer depends on the level of current which is being drawn. There isn't
enough information in the datasheet to say exactly where the boundary might
lie, since the dc parameters are tested unloaded. There's maybe a clue in the
fact that the AD531 linearity is only tested between codes 28 and 1023.

In practise, if you need the output to swing all the way to one or other of the
rails, you refer the load to that rail, causing the current to reduce at the
critical point and allowing the output stage to go all the way to the rail. The
dominant error then will be the offset error of the buffer, which can be
positive or negative and is guaranteed <3% of full scale (150mV @ 5V full
scale). If the offset is negative then the output won't be able to reach the
positive supply rail (Vref = Vdd), if the offset is positive the output won't
be able to reach GND.
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