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AD5662: Output Buffer does not reach the Rails at nanoDac and add additional FSR Erroro - related to ALL nano Dacs with Voltage Output Buffer

The Output buffer of the AD5662 is specified Output Voltage Range in the
datasheet (Rev A 12_2010) from 0 to Vdd. In my single Supply System (Vdd=5V) I
cannot reach the GND (all "0") nor the Vdd (all "1") loaded into the DAC.


Based on some recent discussions regarding CN0202, CN0203, and CN0204, we have
discovered some well hidden secrets of the single-supply nanoDAC family, such
as the AD5662 (data sheet attached).

The core of the DAC is a “string DAC”, and this is followed by an internal
buffer amplifier to give a voltage output.

The output op amp is single-supply and can only come within a few mV of the +5V
rail and GND. This is just a law of physics. You can’t make a rail-to-rail
output stage go all the way to the rails.

This creates an error and the all zeros and all ones codes.

The output voltage for all zeros is called “Zero Code Error” in the data sheet,
and is typically +2mV to +10mV max.  This is because a single supply op amp
cannot go all the way to GND. For 16 bits, and a 5V output range, this is
(10/5000) x 65536 = 131 LSBs, or 0.2% .

The error at all ones code is called “Full Scale Error” and is typically
-0.2%FS from the data sheet, or -10mV, which is also -131 LSBs.

You might be curious about what this does to INL and DNL specifications at the
upper and lower ends of the range. The answer is NOTHING, because there is a
small Note 2 after “STATIC PERFORMANCE” in the specification table which states

“DC specifications are tested with the outputs unloaded, unless otherwise
stated. Linearity is calculated using a reduced code range of 512 to 65024”.
Very clever, huh?  This “reduced code range” eliminates about 40mV (0.8%) at
either end of the range which where the op amp starts to limit.

The “offset error” of a unipolar DAC is generally defined as the output voltage
for the all zero input code, but for the AD5662, it is defined on p. 13 of the
AD5662 data sheet:

“Offset error is a measure of the difference between VOUT (actual) and VOUT
(ideal) expressed in mV in the linear region of the transfer function. Offset
error is measured on the AD5662 with Code 512 loaded in the DAC register. It
can be negative or positive.”

So the bottom line is the upper and lower 0.8% of the range of the DAC is not
included in the DC INL, DNL, and TUE specifications.

There’s nothing at all wrong with defining the specs this way, because in a
single supply system, customers can’t usually utilize the upper and lower parts
of the range anyhow.

Maybe all of you knew this, and I’m just learning about it now. If so, just
ignore the email. 

It is a really clever use of “honest specsmanship” to get around a problem
without calling attention to it.