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AD5421 Si revisions and influence on HART tests
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AD420: Accuracy of Vout
AD420: Maximum output current and maximum current absorption
AD420: Output voltage range
AD420_external current boost transistor
AD421 data input interfacing with optocoupler
AD5024: Operating temperature of evaluation boards
AD5060 Ground Voltages
AD5065 t7 maximum timing
AD5111, AD5113, AD5115: Shutdown mode
AD5142 - IBIS File
AD5161: Error in equation 4 / effect of wiper resistance, VW
AD5203: Negative voltage at the output
AD5222: Absolute maximum ratings, latchup, zero code resistance and distortion
AD5222: Residual audio signal
AD5232 Daisy Cain Mode Issues
ad5232: Connection of VSS
AD5232: Daisy chain
AD5235: Daisy chain
AD5243 VOL output logic level
AD5248 fuse bit / power up at midscale
AD524: Thermal resistance
AD524: Theta JA(Junction to Ambient Temperature) and Theta JC (Junction to case Temperature)
AD524: Working in a strong magnetic field
AD5251, AD5252, Theta JC Values
AD5252 I2C pins on VDD+0.3V
AD5252: Channal matching
AD5254 - different VDD and I2C bus voltage
AD5258 datasheet shows how to calculate RWA and RWB. These AD5258 data sheet max Rwb query
AD5259 - "Not Connected Option - third logical stage "1", "0", "NC" ??
AD5259 I2C Device Address
AD5263, connection of Digital Pot SHDN Pin 15
AD527x resistance calculation
AD527x, how to measure the resistance value of digipot
AD5290: Nominal resistance
AD5292: SPI Mode issues
AD5293: shift register DIN with MSB first or least?
AD5301 Signal Accuracy and Absolute Error
AD5301: Reference usage
AD5318: locked status due to power on
AD5321_I2C level translator
AD5331: output voltage range and reduced output swing with greater loading
AD5338: Difference in offset between channel 1 and channel 2 of the AD5338
AD53500: Thermal questions
AD5363 AD5362_SPI communication with Blackfin processor
AD536: Using a potential divider
AD5370: Data Input Format
AD5383-5 maximum current that can be supplied by each voltage output?
AD5383: Pin connections
AD5405_four quadrant resistors
AD5412 output voltage range
AD5420 using an external resistor RSET
AD5420: ASYNCHRONOUS CLEAR Function
AD5420: fault flag state is indeterminate when digital power is applied first.
AD5420: What happens to output current if supply voltage drops below 10.8V, at what point is shutdown?
AD5421 Si revisions and influence on HART tests
AD5422 - Connecting multiple DVCC outputs together
AD5422: 3 pin SPI interface
AD5422: HART compatability
AD5422: What is the role of R27 Socket in AD5422's EVB?
AD5422_SPI daisy chain reading
AD5429: DAC not responding to sending of serial word
AD5439: crosstalk problem
AD5440 - Pin out query
AD5449 mixed mode DACloading query
AD5449: Output noise spectral density
AD548B replacement is ADA4062
AD549: Higher noise
AD549: Noise problem
AD5522 Evaluation Board kit documenation does not match datasheet Rev E?
AD5546: reference input circuit
AD5553 Operating Temperature
AD5554: Bias over temperature
AD5554: Current circuit
ad557: Maximum output current
AD5623R CLR pin
AD5640: Increasing gain
AD565A: did a AD565A/BIN exist?
AD5662: Output Buffer does not reach the Rails at nanoDac and add additional FSR Erroro - related to ALL nano Dacs with Voltage Output Buffer
AD5696R I2C SDA stuck on GND
AD5700 logic signal isolation
AD5700: HART Manufacturing ID
AD5722R, NC pins have 2 additional working DAC channel outputs (same as AD5724R)
AD574: Maximum ratings for 10V input
AD5750 hardware mode OUTEN
AD5750-1: Can the software determine which variant of AD5750 is populated -1 or -2?
AD5755_vsense connection_DCDC_transfer function
AD5764_SYNC pin as CS.
AD5791 daisy chain
AD5791 question re Gain of Two Configuration
AD5791: Recommended reference
ad667: If CS\=0 are input latches transparent
AD667: supply voltage
AD688_internal resistors value
AD698 becoming hot
AD698 power supply current calculation
AD698 Supply Voltage versus Output Voltage
AD698: 6 wire sensor connection
AD698: Lead/lag pins
AD698: Maximum input at A and B input
AD698: phase lead / phase lag compensation
AD698: Power supply
AD698: Power supply +/-12V
AD698: R3 calculation error in datasheet phase lead phase lag compensation
AD8403: Connecting to digital
AD9913 interfacing circuit
ADG506ATE/883B operating temperature and thermal resistance in Leadless Ceramic Chip Carrier Package
Alternative FET recommendation for AD421
Bandwidth of buffer and IC
Bandwidth of the Singal that can be Measured by the Comparator
Can DAC SPI pins be left floating for a while before the micro is configured
Can multiple AD5660 devices be updated simultaneously?
Can you confirm 2's Complement coding in Table 14 of AD5724 datasheet Rev. D?
CN0336: Where can I find a solution for a receiver in a 4-20mA current loop sensor application?
Connect the AD5412/AD5422's Iout and Vout pins directly together
connection to the Exposed Pad of the Chip Scale Package for AD5664?
Current loop and HART with 4 channels
Daisy chaining AD5271 and ADG714 possibility
Daisy Chaining AD532x parts
Datasheet output noise, figures 45, 46 and 47 labelled incorrectly
DEMO-AD5700D2Z kit : Finding a low cost IDE
Digital potentiometer: Rheostat mode: Bandwidth calculation
Do the AD5254 adjustable resistors have galvanic isolation?
Does AD5245 (Potentiometer) have a log or linear taper?
Error in Figure 32 - 2-wire serial bus
EVAL-AD5791SDZ for arbitrary function generators
Eval-ADUCM360QSPZ + Demo-AD5700D2Z
FAQ: AD5421 Supply Pin Configuration
FAQ: How Does the PEC Function Work in AD536x DACs?
FAQ: Selecting A Reference for the AD536x and AD537x DACs
FAQ: Selecting An Output Range for the AD536x and AD537x DACs
FAQ: Using the m and c Registers on AD536x and AD537x DACs
FAQ: Using the Offset Register in AD536x and AD537x DACs
FAQ: X1A and X1B Registers in the AD536x and AD537x DACs
FAQs: DAC Communication Troubleshooting
FAQs: DAC Daisy Chain
FAQs: DAC Power-up sequence and Biasing
How often can I write to the AD5141's internal EEPROM?
Intrinsic safety - voltage / capacitance minimizing
Is AD5556 usable without negative voltage?
Is there an AD693 RoHS version?
Key differences in specification between the AD674BBD and BTD grades
Labview Error 1172 (.NET exception) when starting AD5780 evaluation software
LDC - Pin connections - continuos V out
long term drift over time
Maximum Current Density
nanoDAC+ Family AD531x/AD568x/AD569x/AD567x FAQ
Offset Adjustment and Gain Adjustment
Operation below 2.3VDD
Power Supply Rails
Power Supply Sequence
PRECISION DAC SUPPORT COMMUNITY
Problem with HART Modem
Pull-up / Pull-down resistors
Purpose of the switch on the RTS - HART_OUT line
schematic diagram to control AD9913
Setting up the AD5755
The AD5420/AD5422 does not seem to function as I expect when using external RSET?
The maximum acceptable clock rise time for the AD5160's reliable operation?
Thermal Analysis Data
Thermal resistance value of AD5755
unused SDO output to tie or not to tie or leave it open that is the question
Using SYNC as a Chip Select Pin
Using the AD5755 family in Applications Without Dynamic Power Control
Using toggle mode in the AD5384 using an I2C interface
VDD and VLOGIC
What is the maximum junction temperature of AD698 or the maximum permissible power dissipation?
What type of non-volatile memory hast the AD5270? What is its retention time?
Where can I find the tape width for a tape reel of devices ?
Which package device is populated on the AD5669RSDZ eval board?
AD5421 Si revisions and influence on HART tests
I try to finalize our development with AD5700 connected to AD5421. Therefore I
am now on the way to fulfill the HART Hardwarelayer specifications. I did the
Physical-layer-test from the HART-Foundation (official document “Test-2.pdf”
Rev 2.2) several times with nearly the same circuit like the “AD5700D2Z demo
board” but my circuit uses the suggested transistor for power reduction on the
AD5421 (suggested in the datasheet of the AD5421).
The suggested circuit on the “AD5700D2Z demo board” uses a 4.7nF capacitor for
I have five pcb-prototypes and all boards have problems with the “noise in
HART-bandwidth test (official test number 13.4 “Output Noise During Silence” in
the official document “Test-2.pdf”) when using only the 4.7nF.
All boards show a RMS noise value of something near to 24mVRMS behind the
HCF_Tool-31. That’s too high because 22mVRMS is only allowed. First I wondered
about the result and checked a lot of things (also I did a FFT-analysis of all
paths coming out of the AD5421).
What I have also find out is, that the lower the quiescent current flowing in
the loop the higher the noise will be. We have in HART-Mode a minimum current
of 3,5mA flowing and the 24mVRMS is measured always at this current flowing.
Not passing the test 13.4 for me means to build an own noise reduction filter.
I did this but now I have to use nearly 22nF. So the capacitance on the
HART-bus is now nearly 22nF instead the suggested 5nF in Test 13.6 in the
My investigation with my five pcb-prototypes leads to nothing further like:
well it is like it is…we need 22nF.
Today I have discovered something interesting:
The AD5421 is already used in another project without the AD5700 connected to
it (just current loop option). I desoldered one AD5421 out of this pcb and
soldered the device onto one of my five pcb-prototypes. I did the measurement
again and I was very surprised (and I am still surprised about this
measurement!). The result was an RMS value of nearly 11mVRMS!!!!!!!!!! That
correlates with results you sent me from the “AD5700D2Z demo board” in document
The conclusion for me is: something has changed in the silicon. I compared the
labels and they are different indeed.
The AD5421BREZ which works and satisfy our needs has the code “#1319” written
on the surface.
The AD5421BREZ which doesn’t satisfy our needs has the code “#1133” written on
I also checked an AD5421CREZ with the code “#1049” and it was more worse than
The question now is: Were there changes within the silicon to lower the output
noise? How could be guaranteed that all AD5421 we will use have the same “noise
output” like the “#1319” when using 4.7nF output capacitance?
Could you be pleased to help me soon about that problem?
I am pleased to hear something from you urgently, because I can not finish the
project without the answered questions.
My project is in the way to be finished, when we get the satisfied answers and
there is some pressure to finish the project as soon as possible.
YES, there has been change to the AD5421 silicon.
And the change was actually initiated by the DEMO-AD5700D2Z evaluation and HART
tests. A PCN was issued on December 19th, 2011 for a minor metal edit to the
AD5421. The PCN can be accessed on the web from column 9 of the ordering guide
at the bottom of the product page:
This is effective from date code 1138 onwards (#1138 package marking means the
date code 2011 Week 38).
And yes, it agrees with our measurements, the lower the output current, the
higher the noise level. We used 4mA for our test results. We were probably
checking at the alarm current level as well, but I would have to dig deep to
find out whether we do have data for <4mA or not.
BTW, the 22nF capacitance would still be OK, especially if the device is
planned but it is very strongly recommended not to go any higher.
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