Q
I try to finalize our development with AD5700 connected to AD5421. Therefore I
am now on the way to fulfill the HART Hardwarelayer specifications. I did the
Physical-layer-test from the HART-Foundation (official document “Test-2.pdf”
Rev 2.2) several times with nearly the same circuit like the “AD5700D2Z demo
board” but my circuit uses the suggested transistor for power reduction on the
AD5421 (suggested in the datasheet of the AD5421).
The suggested circuit on the “AD5700D2Z demo board” uses a 4.7nF capacitor for
noise reduction.
I have five pcb-prototypes and all boards have problems with the “noise in
HART-bandwidth test (official test number 13.4 “Output Noise During Silence” in
the official document “Test-2.pdf”) when using only the 4.7nF.
All boards show a RMS noise value of something near to 24mVRMS behind the
HCF_Tool-31. That’s too high because 22mVRMS is only allowed. First I wondered
about the result and checked a lot of things (also I did a FFT-analysis of all
paths coming out of the AD5421).
What I have also find out is, that the lower the quiescent current flowing in
the loop the higher the noise will be. We have in HART-Mode a minimum current
of 3,5mA flowing and the 24mVRMS is measured always at this current flowing.
Not passing the test 13.4 for me means to build an own noise reduction filter.
I did this but now I have to use nearly 22nF. So the capacitance on the
HART-bus is now nearly 22nF instead the suggested 5nF in Test 13.6 in the
document “Test-2.pdf”.
My investigation with my five pcb-prototypes leads to nothing further like:
well it is like it is…we need 22nF.
Today I have discovered something interesting:
The AD5421 is already used in another project without the AD5700 connected to
it (just current loop option). I desoldered one AD5421 out of this pcb and
soldered the device onto one of my five pcb-prototypes. I did the measurement
again and I was very surprised (and I am still surprised about this
measurement!). The result was an RMS value of nearly 11mVRMS!!!!!!!!!! That
correlates with results you sent me from the “AD5700D2Z demo board” in document
“frm156-2_Physical_layer_test_AD5700D2Z_111123.pdf”.
The conclusion for me is: something has changed in the silicon. I compared the
labels and they are different indeed.
The AD5421BREZ which works and satisfy our needs has the code “#1319” written
on the surface.
The AD5421BREZ which doesn’t satisfy our needs has the code “#1133” written on
the surface.
I also checked an AD5421CREZ with the code “#1049” and it was more worse than
the “#1133”.
The question now is: Were there changes within the silicon to lower the output
noise? How could be guaranteed that all AD5421 we will use have the same “noise
output” like the “#1319” when using 4.7nF output capacitance?
Could you be pleased to help me soon about that problem?
I am pleased to hear something from you urgently, because I can not finish the
project without the answered questions.
My project is in the way to be finished, when we get the satisfied answers and
there is some pressure to finish the project as soon as possible.
A
YES, there has been change to the AD5421 silicon.
And the change was actually initiated by the DEMO-AD5700D2Z evaluation and HART
tests. A PCN was issued on December 19th, 2011 for a minor metal edit to the
AD5421. The PCN can be accessed on the web from column 9 of the ordering guide
at the bottom of the product page:
http://www.analog.com/en/digital-to-analog-converters/da-converters/ad5421/produ
cts/product.html
This is effective from date code 1138 onwards (#1138 package marking means the
date code 2011 Week 38).
And yes, it agrees with our measurements, the lower the output current, the
higher the noise level. We used 4mA for our test results. We were probably
checking at the alarm current level as well, but I would have to dig deep to
find out whether we do have data for <4mA or not.
BTW, the 22nF capacitance would still be OK, especially if the device is
planned but it is very strongly recommended not to go any higher.
