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Low Power RF Transceivers
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Wireless Sensor Networks Reference Library
AD698: Lead/lag pins
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AD420: Accuracy of Vout
AD420: Maximum output current and maximum current absorption
AD420: Output voltage range
AD420_external current boost transistor
AD421 data input interfacing with optocoupler
AD5024: Operating temperature of evaluation boards
AD5060 Ground Voltages
AD5065 t7 maximum timing
AD5111, AD5113, AD5115: Shutdown mode
AD5142 - IBIS File
AD5161: Error in equation 4 / effect of wiper resistance, VW
AD5203: Negative voltage at the output
AD5222: Absolute maximum ratings, latchup, zero code resistance and distortion
AD5222: Residual audio signal
AD5232 Daisy Cain Mode Issues
ad5232: Connection of VSS
AD5232: Daisy chain
AD5235: Daisy chain
AD5243 VOL output logic level
AD5248 fuse bit / power up at midscale
AD524: Thermal resistance
AD524: Theta JA(Junction to Ambient Temperature) and Theta JC (Junction to case Temperature)
AD524: Working in a strong magnetic field
AD5251, AD5252, Theta JC Values
AD5252 I2C pins on VDD+0.3V
AD5252: Channal matching
AD5254 - different VDD and I2C bus voltage
AD5258 datasheet shows how to calculate RWA and RWB. These AD5258 data sheet max Rwb query
AD5259 - "Not Connected Option - third logical stage "1", "0", "NC" ??
AD5259 I2C Device Address
AD5263, connection of Digital Pot SHDN Pin 15
AD527x resistance calculation
AD527x, how to measure the resistance value of digipot
AD5290: Nominal resistance
AD5292: SPI Mode issues
AD5293: shift register DIN with MSB first or least?
AD5301 Signal Accuracy and Absolute Error
AD5301: Reference usage
AD5318: locked status due to power on
AD5321_I2C level translator
AD5331: output voltage range and reduced output swing with greater loading
AD5338: Difference in offset between channel 1 and channel 2 of the AD5338
AD53500: Thermal questions
AD5363 AD5362_SPI communication with Blackfin processor
AD536: Using a potential divider
AD5370: Data Input Format
AD5383-5 maximum current that can be supplied by each voltage output?
AD5383: Pin connections
AD5405_four quadrant resistors
AD5412 output voltage range
AD5420 using an external resistor RSET
AD5420: ASYNCHRONOUS CLEAR Function
AD5420: fault flag state is indeterminate when digital power is applied first.
AD5420: What happens to output current if supply voltage drops below 10.8V, at what point is shutdown?
AD5421 Si revisions and influence on HART tests
AD5422 - Connecting multiple DVCC outputs together
AD5422: 3 pin SPI interface
AD5422: HART compatability
AD5422: What is the role of R27 Socket in AD5422's EVB?
AD5422_SPI daisy chain reading
AD5429: DAC not responding to sending of serial word
AD5439: crosstalk problem
AD5440 - Pin out query
AD5449 mixed mode DACloading query
AD5449: Output noise spectral density
AD548B replacement is ADA4062
AD549: Higher noise
AD549: Noise problem
AD5522 Evaluation Board kit documenation does not match datasheet Rev E?
AD5546: reference input circuit
AD5553 Operating Temperature
AD5554: Bias over temperature
AD5554: Current circuit
ad557: Maximum output current
AD5623R CLR pin
AD5640: Increasing gain
AD565A: did a AD565A/BIN exist?
AD5662: Output Buffer does not reach the Rails at nanoDac and add additional FSR Erroro - related to ALL nano Dacs with Voltage Output Buffer
AD5696R I2C SDA stuck on GND
AD5700 logic signal isolation
AD5700: HART Manufacturing ID
AD5722R, NC pins have 2 additional working DAC channel outputs (same as AD5724R)
AD574: Maximum ratings for 10V input
AD5750 hardware mode OUTEN
AD5750-1: Can the software determine which variant of AD5750 is populated -1 or -2?
AD5755_vsense connection_DCDC_transfer function
AD5764_SYNC pin as CS.
AD5791 daisy chain
AD5791 question re Gain of Two Configuration
AD5791: Recommended reference
ad667: If CS\=0 are input latches transparent
AD667: supply voltage
AD688_internal resistors value
AD698 becoming hot
AD698 power supply current calculation
AD698 Supply Voltage versus Output Voltage
AD698: 6 wire sensor connection
AD698: Lead/lag pins
AD698: Maximum input at A and B input
AD698: phase lead / phase lag compensation
AD698: Power supply
AD698: Power supply +/-12V
AD698: R3 calculation error in datasheet phase lead phase lag compensation
AD8403: Connecting to digital
AD9913 interfacing circuit
ADG506ATE/883B operating temperature and thermal resistance in Leadless Ceramic Chip Carrier Package
Alternative FET recommendation for AD421
Bandwidth of buffer and IC
Bandwidth of the Singal that can be Measured by the Comparator
Can DAC SPI pins be left floating for a while before the micro is configured
Can multiple AD5660 devices be updated simultaneously?
Can you confirm 2's Complement coding in Table 14 of AD5724 datasheet Rev. D?
CN0336: Where can I find a solution for a receiver in a 4-20mA current loop sensor application?
Connect the AD5412/AD5422's Iout and Vout pins directly together
connection to the Exposed Pad of the Chip Scale Package for AD5664?
Current loop and HART with 4 channels
Daisy chaining AD5271 and ADG714 possibility
Daisy Chaining AD532x parts
Datasheet output noise, figures 45, 46 and 47 labelled incorrectly
DEMO-AD5700D2Z kit : Finding a low cost IDE
Digital potentiometer: Rheostat mode: Bandwidth calculation
Do the AD5254 adjustable resistors have galvanic isolation?
Does AD5245 (Potentiometer) have a log or linear taper?
Error in Figure 32 - 2-wire serial bus
EVAL-AD5791SDZ for arbitrary function generators
Eval-ADUCM360QSPZ + Demo-AD5700D2Z
FAQ: AD5421 Supply Pin Configuration
FAQ: How Does the PEC Function Work in AD536x DACs?
FAQ: Selecting A Reference for the AD536x and AD537x DACs
FAQ: Selecting An Output Range for the AD536x and AD537x DACs
FAQ: Using the m and c Registers on AD536x and AD537x DACs
FAQ: Using the Offset Register in AD536x and AD537x DACs
FAQ: X1A and X1B Registers in the AD536x and AD537x DACs
FAQs: DAC Communication Troubleshooting
FAQs: DAC Daisy Chain
FAQs: DAC Power-up sequence and Biasing
How often can I write to the AD5141's internal EEPROM?
Intrinsic safety - voltage / capacitance minimizing
Is AD5556 usable without negative voltage?
Is there an AD693 RoHS version?
Key differences in specification between the AD674BBD and BTD grades
Labview Error 1172 (.NET exception) when starting AD5780 evaluation software
LDC - Pin connections - continuos V out
long term drift over time
Maximum Current Density
nanoDAC+ Family AD531x/AD568x/AD569x/AD567x FAQ
Offset Adjustment and Gain Adjustment
Operation below 2.3VDD
Power Supply Rails
Power Supply Sequence
PRECISION DAC SUPPORT COMMUNITY
Problem with HART Modem
Pull-up / Pull-down resistors
Purpose of the switch on the RTS - HART_OUT line
schematic diagram to control AD9913
Setting up the AD5755
The AD5420/AD5422 does not seem to function as I expect when using external RSET?
The maximum acceptable clock rise time for the AD5160's reliable operation?
Thermal Analysis Data
Thermal resistance value of AD5755
unused SDO output to tie or not to tie or leave it open that is the question
Using SYNC as a Chip Select Pin
Using the AD5755 family in Applications Without Dynamic Power Control
Using toggle mode in the AD5384 using an I2C interface
VDD and VLOGIC
What is the maximum junction temperature of AD698 or the maximum permissible power dissipation?
What type of non-volatile memory hast the AD5270? What is its retention time?
Where can I find the tape width for a tape reel of devices ?
Which package device is populated on the AD5669RSDZ eval board?
AD698: Lead/lag pins
I have Used AD598 for many years but as the LVDT coils are not linear I have
switched to AD698 in conjunction with the data sheet. I have not fitted any
components for Lead/Lag and get not DC output Will the IC work with these open
circuit? The data sheet gives no info are this, what is the basic values if I
require no compensation? I have made provision on the board for either
configuration but have left all parts open circuit.
The values used for the R and C of the phase compensation circuit depend
entirely on the phase shift
introduced by your LVDT, at the frequency of operation. This is not listed in
the LVDT datasheet and
should be checked using a scope to observe the inputs and outputs of the LVDT.
I can however explain
to you the reason for the phase compensation circuit and this should assist you
in choosing your values
when you have determined the phase shift.
To explain the phase compensation circuit I will refer you to the block diagram
on page 5, fig 6, of the
datasheet. If you look at both A and B channels you can see that there is a V/I
block and a comparator
block on each. In both cases what is happening is that the input sinewave is
being full wave rectified,
using the comparator to find the zero crossings of the input sinewave and using
this information to either
pass or invert the output of the V/I block. Both channels are then filtered,
using the external C2 & C3 caps
and a duty cycle based on the ratio of the amplitudes of the rectified inputs
is set up.
However, when using a series opposed LVDT the amplitude of the A channel input
reduces to zero at
the null point of the LVDT. The A channel input itself should not be used to
rectify itself as it will be
prone to errors. Because of this we include the Acomp inputs, which are taken
either directly from the
B inputs, which are constant amplitude, or which are phase adjusted versions of
the B inputs. The
phase should be adjusted such that the phase of the Acomp inputs matches that
of the A inputs. In
many cases setting the values of the phase lead/lag components does come down
to some trial and
error when initially setting up the AD698. This is simply done using a scope to
overlay the Acomp and
A channels, usually when the LVDT is at either end point, of the linear range,
not the null point. If there
is a phase difference between the channels simply adjust either one of the cap
or the resistor values
until the signal match up. Using a pot as suggested in the diagram does speed
this process up and the
pot can then be replaced by the equivalent resistor value in a final setup.
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