AD8403 on the same SPI bus while giving a uniq CS for each chip (not a daisy
So all SDI's connected to the controller's output signal, all CLK's connected
to the clk signal, and all the SDO's connected to the controller's input signal.
By so the pot. is determines by the 2 address bits and the appropriate CS.
Connecting CLK and SDI together and using the /CS pin to arbitrate between
Connecting the SDO lines together, you need to be careful. The SDO line is an
open drain output and requires a pull-up resistor - SDO does not tri-state.
Connecting all SDO lines together will create a "wired OR" configuration. After
/CS goes high, SDO will retain the state of the last bit clocked into SDI, and
this could be zero or one. If any of the SDO lines are low, it will pull all
the other SDO lines low. This will not damage the parts but will prevent you
from reading back data on the SDO line.
Use Daisy Chaining.
Do not readback on SDO
Ensure the the last bit (D0) written to SDI prior to /CS is always a one - this
will mean you can only use 128 steps instead of 256.