What is the delay when transitioning between two output values?

The delay specification is captured within the output settling time of the MAX5100 DAC. Per Note 3, the output settling time is measured from the 50% point of the falling edge of WR to 1/2LSB of Vout's final value. This includes the delay from writing to the input registers, and the delay from making the DAC latches transparent. Normally, the input registers are continuously updated, so this specification is written from the falling edge of WR.  The delay is typically 6us when transitioning from 0x10 to 0xF0.