Question:
- Wjhat is the priority list of the I/O configuration register settings?
- If I configure the channel 1 as both an ADC and DAC, can the ADC read back the voltage at the I/O pin 1 with whatever has been set by the DAC?
- Is there any conflict having multiple configurations on the same I/O channel?
Answer:
As reproduced from the datasheet, page 27, second column
In the event that the bit for an input/output channel is set in multiple configuration registers, the input/output channel takes the function dictated by the last write operation. The exceptions to this rule are that an I/Ox pin can be set as both a DAC and an ADC or as a digital input and output. When an I/Ox pin is configured as a DAC and ADC, its primary function is as a DAC, and the ADC can measure the voltage being provided by the DAC. This feature can monitor the output voltage to detect short circuits or overload conditions.
When a pin is configured as both a general-purpose input and output, the primary function is as an output pin. This configuration allows the status of the output pin to be determined by reading the GPIO register. Figure 43 shows a typical configuration example where I/O0 and I/O1 are configured as ADCs, I/O2 and I/O3 are configured as DACs, I/O4 is a general-purpose output pin, I/O5 is a general-purpose input pin, and I/O6 and I/O7 are three-state.
Do note that while applying multiple configurations on the same I/O channel, if the GPIO or other non-ADC/DAC configuration registers are updated between the DAC and the ADC configuration registers for the same I/O channel, it is the last DAC or the ADC configuration register that will be effected and not both the ADC and the DAC configuration registers. For example, if the configuration settings are as follows:
SOFTWARE_RESET_REG --> 0x0D 0xAC
POWER_DOWN_REF_CTRL_REG --> 0x02 0x00
GEN_PURP_CTRL_REG --> 0x03 0x00
DAC_PIN_CFG_REG --> 0x00 0xC0
PULL_DOWN_CFG_REG --> 0x00 0x00
GPIO_WR_CFG_REG --> 0x00 0x00
GPIO_RD_CFG_REG --> 0x00 0x00
GPIO_OPEN_DRAIN_CFG_REG 0x00 0x00
THREE_STATECFG_REG --> 0x00 0x00
ADC_PIN_CFG_REG --> 0x00 0x3F
NOP_REG --> 0x00 0x00
In the above example, DAC_PIN_CFG_REG will be nullified by the PULL_DOWN_CFG_REG on the I/O channels 6 and 7. So, any update to the DAC register will be ignored for the channels 6 and 7. To ensure that it happens correctly, it is preferrable to have DAC_PIN_CFG_REG immediately before or after the ADC_PIN_CFG_REG in the above example.