I noticed an unexpected AD5592R behavior of the chip during a read of multiple ADC channels. According to the Datasheet (Figure 47. Multichannel ADC Conversion Sequence, No Repeat) the SPI-Master has to follow the following sequence when reading a sequence of two ADC channels:
- Write to ADC Sequence Register to enable two ADC channels
- NOP register write
- Write NOP, Read channel conversion result of the first selected ADC channel in the sequence
- Write NOP, Read channel conversion result of the second selected ADC channel in the sequence
The behavior I observe is, that the result of the first selected ADC in the sequence is clocked out in step 2 and NOT in step 3 which is not in accordance with the figure 47 in the datasheet. Can you explain this behavior?
There is a timing parameter t4 in Table 3 and Table 4 in the datasheet. It represents the time from the /SYNC falling edge to the first falling edge of SCLK when the ADC conversion is enabled through the ADC Sequence Register as shown in Figure 5 in the datasheet.
If in any frame undergoing the ADC conversion, the first falling edge of SCLK will happen later than t4 from the /SYNC falling edge, which violates the t4 parameter, the ADC conversion result is clocked out in the same frame.
No matter what the SCLK frequency is, the t4 timing parameter must be enforced for the successful ADC conversion. It is also recommended to read back the ADC channel address with every ADC conversion result.