Hi all,
We and our customer are confused for Vout status.
When VDD and VREF supply, what initial status are the Vout and DAC Latch @ AD7228A ?
In "Figure 2. Write Cycle Timing Diagram",
"NOTE:
THE SELECTED INPUT LATCH IS TRANSPARENT WHILE WR IS LOW,
THUS INVALID DATA DURING THIS TIME CAN CAUSE SPURIOUS OUTPUTS."
This means that initial Vout status is undefined ?
Best regards,
sss
Hi sss,
Someone is currently looking into this thread and will give a reply to you the soonest possible time.
Cheers,
Ivan
Hi sss,
To answer your second question, the VOUT is defined by the input data while WR is low. This behavior is applicable not just at initial power up, but even after that.
Just want to ask, what is…
Hi sss-san,
Given that AD7228 is a very old part which probably does not have a POR circuit, the device might power up in unknown state.
Cheers,
Ivan
