We and our customer are confused for Vout status.
When VDD and VREF supply, what initial status are the Vout and DAC Latch @ AD7228A ?
In "Figure 2. Write Cycle Timing Diagram",
THE SELECTED INPUT LATCH IS TRANSPARENT WHILE WR IS LOW,
THUS INVALID DATA DURING THIS TIME CAN CAUSE SPURIOUS OUTPUTS."
This means that initial Vout status is undefined ?