Hello, i am using the AD5692R with I2C-Interface. I write the data to the DAC by sending 4 bytes via I2C with 600 kHz I2C-clock.
Because of timing-restrictions in the host-cpu the cpu holds the clock-line low after 2 first 2 bytes of the 4-byte transmission. After 200 µs the host continues the communication and writes the other 2 bytes into the DAC.
I already tested these procedure and it works with my actual timings. I have added a scope picture with the transmission of the 4 byte.
My Question is: Can i rely that the AD5692R will always accept these 4 Bytes as 1 command. Or is there any time limit or time out when the AD5692R will discard the first 2 Bytes?
There is no SCL time out limit for AD5692R and will still accept all 4 bytes, however, I noticed that the 600 kHz SCL frequency you used is above the 400 kHz limit (with conditions) which we can guarantee.
Thank you for the fast reply, yes i've seen the restrictions. Can you tell me if the kind of clock stretching will work on all Analog Devices ICs with I2C interface or at least some product groups with these feature. Might be very helpful for further developments.
I can't speak for other ADI products but for Precision DACs, I am haven't seen anything with this kind of limitation.